Recent research has shown that Network on-chip (NoC) is superior to a bus in terms of power and area for given traffic throughput requirements. Consequently, NoC is expected to be the main interconnect infrastructure in future System on Chip (SoC) and chip multi-processor (CMP). Unlike off-chip networks, VLSI modules are only a few millimeters apart, hence the cost of off-network communication ...

In this paper, a new method based on branch placement for the optimal positioning of Phasor Measurement Units (PMUs) in power systems is proposed. In this method, the PMUs are in type of single-channel and are installed at the beginning of the branches. Therefore, they are able to measure the bus voltages. Also, the installation of the PMUs on the branches increases the security of observabilit...

Introduction: Everyday urban mobility is fundamental to access the opportunities offered by cities, something required to accomplish one’s own aims and guarantee participation in social life. Nonetheless, it is difficult to guarantee significant individual opportunities by fighting mobility-related social exclusion, especially in Global South cities characterized by scarce provision of mobility...

The bus network design problem is an important problem in transportation planning. It is the problem of determining a network of bus lines which best achieves a predetermined objective. This may be done with or without the presence of rapid transit lines. This study is devoted to solving this problem using genetic algorithm. The fitness function is defined as the benefit to the users of the bus...

Network on-chip (NoC) is a novel structural design template, which can be defied for complicated system level on-chip design. NoC has a potential to limit and present the bus-based communication. In this paper, the crisis to discuss is Low power consumption in an Asynchronous Network on-chip (NoC) level communication. NoC is implemented using FPGA which has less fabrication cost and reduces the...

Single bus multiprocessor systems do not scale well due to the limited bandwidth of the bus. Hierarchical bus interconnections are scalable, but unfortunately the top level bus becomes a bottleneck for larger systems. In this paper we present a novel interconnection network called the Multistage Bus Network(MBN). The MBN consists of multiple stages of buses and it preserves the bandwidth proper...

The present paper deals with the transit network design problem related to the feeder bus lines defined as transit services for connecting suburban areas, where the demand has to be gathered, with the stops of the mass transit network, usually railway or underground stations. The objective of the research is the development of a procedure that simultaneously generates routes and frequencies of ...