This paper aims at closing the gap between early phases (e.g. design) and later phases (e.g. procurement or production) of the Product Development Process (PDP) by proposing a Virtual Product Model (VPM) as a collection of individual components (VPMCs) without the need for a static structure. Based on an analysis of the requirements on product development in the automotive industry, the main pr...

In this paper, we study the effects of the variations of the propagation delay over large-scale antenna-arrays used in massive multiple-input multiple-output (MIMO) wideband communication systems on the statistical properties of the channel. Due to its simplicity and popularity, the Elliptical geometry-based stochastic channel model (GBSM) is employed to demonstrate new non-stationary propertie...

A new side-contacted field effect diode (S-FED) structure has beenintroduced as a modified S-FED, which is composed of a diode and planar double gateMOSFET. In this paper, drain current of modified and conventional S-FEDs wereinvestigated in on-state and off-state. For the conventional S-FED, the potential barrierheight between the source and the channel is observed to b...

The continuous scaling down of feature size in Silicon technology has resulted in several technological and fundamental hindrances. The researchers started to look for new nanoscale devices those can replace CMOS transistors in digital circuits. The nanowire transistor, FinFET, Carbon Nanotube field effect transistor (CNFET), tunnel field effect transistor (TFET), and single electron transistor...

This paper proposes a new technique for Mobile IP (MIP) registration by WLAN host (WH) of the Internet through GPRS network. The home agent (HA) of WH resides in the Internet. The gateway GPRS Support Node (GGSN) provides foreign agent (FA) functionality for WH in GPRS. After successful attachment with GPRS network in roaming scenario, WH needs two mandatory passes for MIP registration with HA....

A modified approach for constant delay logic style is developed in this paper to provide improved power and delay named LP-HS logic. Constant delay logic style is examined against the LP-HS logic, by analysis through simulation. It is shown that the proposed LP-HS logic has low power, delay and power delay product over the existing constant delay logic style. Multiplier accumulator unit is one ...

This paper presents a novel low-power and high-speed 1-bit full-adder, which is designed based on pass transistor and TG logics. The main advantage of this design is low propagation delay and lowpower consumption, which leads to achieving lower PDP than others. Intensive HSPICE simulation shows that the new full-adder consumes around 28.5% less power than 14T adder; moreover its PDPis 30% less ...

This paper presents a ternary half adder and 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed pass transistor logic dynamic logic. Ternary uses less connections than binary logic, voltage changes required for the same amount of data transmission. Carbon transistors have advantages over MOSFETs, such as mobility electrons holes, ability to adjust threshold ...

This paper presents different techniques of one bit Full adder. In every technique the main requirements are power consumption, speed and power delay product. The proposed FIN-FET technique gives the bette.r power consumption, speed and power delay product than other techniques. The proposed Fin-FET technique is compared with some of the popular adders based on the power consumption, speed and ...

Addition is a fundamental arithmetic operation which is used in different applications such as digital signal processing (DSP) and microprocessors. Single bit adder is the main component of any arithmetic circuit. This paper presents the design of new split-path Data Driven Dynamic (sp-D3L) full adder circuit. Power consumption of proposed adder varies from 0.584 nW to 2.914 nW with variation i...