We prove an exponential lower bound on the length of cutting plane proofs. The proof uses an extension of a lower bound for monotone circuits to circuits which compute with real numbers and use nondecreasing functions as gates. The latter result is of independent interest, since, in particular, it implies an exponential lower bound for some arithmetic circuits.

Circuit simulation becomes more and important in integrated circuit design. For VLSI circuits, the usually outputs signal waveforms occupying massive storage space. The compression of these crucial to efficiency simulation. Logic mainly values at time transition some auxiliary information such as name, type, width. A method for is proposed. Then, name scheme existing work improved...

Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computer-aided design (CAD) tools has converted wave-pipelining from a theoretical oddity into a realistic, although challengi...

This paper describes the parameter and characteristic analysis of Low power and High speed CMOS Logic Circuits in 90nm Technology. The proposed CMOS logic circuits consists only logic gates. CMOS circuit is fabricated in 0.12μm and 90nm CMOS technology. The supply voltage is 1.20V. The temperature was 27oC. We observed Inverter (NOT gate) properties MOS, Capacitance, Resistance, Inductance and ...

This paper reports on the veriication of two of the IFIP WG10.5 benchmarks | the multi-plier and systolic matrix multiplier. The circuit implementations are timed, detailed gate-level descriptions, and the speciication is given using the temporal logic TL n , a quaternary-valued temporal logic. A practical, integrated theorem-proving/model checking system based on the compositional theory for T...

After a brief review of the characteristics of electrical stress degradation of flexible, amorphous silicon thin film transistors, the implications for various types of flexible circuitry including active matrix backplanes, integrated drivers and general purpose digital circuitry are examined. A circuit modeling tool that enables the prediction of complex circuit degradation is presented. Exper...

In this paper, a novel variable topology for evolutionary hardware design is proposed. The slicing structure and routing graph are integrated into the design of evolutionary hardware. With off-line gate-level samples, simulation results clearly demonstrate the validity of this new approach performed as superior as existing methods in the logic circuit optimization. Compare with the random circu...

This thesis describes the circuit level design of a 900MHz EA ring oscillator based phase-locked loop using 0.35um technology. Multiple phase noise theories are considered giving insight into low phase-noise voltage controlled oscillator design. The circuit utilizes a fully symmetric differential voltage controlled oscillator with cascode current starved inverters to reduces current noise. A co...

Now that the field of automated synthesis for register transfer level integrated circuit design is beginning to mature, it is appropriate to begin developing tools for higher levels of design. At the next higher level, it is appropriate to explore behavioral and structural partitioning, answering such questions about the design as: • Should the design be implemented on a single VLSI chip, or pa...

This paper presents a switch-level test generation system for synchronous sequential circuits in which a new algorithm for switch-level test generation and an existing fault simulator are integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models all aspects of switch-level behavior. The time-frame based algorithm uses asynchronous processing wit...