to enhance the closed loop performance in presence of disturbance, uncertainties and delay a double loop mixture of mpc and robust controller is proposed. this double loop controller ensures smooth tracking for a 3-axis gyro-stabilized platform which has delay intrinsically. this control idea is suggested to eliminate high frequency disturbances and minimize steady state error with minimum powe...

this paper presents h∞ control problem for input-delayed systems. a neutral system approach is considered to the design of pd controller for input delay systems in presence of uncertain time-invariant delay. using this approach, the resulting closed-loop system turns into a specific time-delay system of neutral type. the significant specification of this neutral system is that its delayed coeff...

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (~25ps – 800ps binning) and a dynamic range of 102.4μs has been implemented in a 0.25μm CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time...

Speed estimation schemes based on the closed-loop synchronization (CLS) methods for speed-sensorless control of motor drives attract much popularity due to several advantages, example, easy implementation, high flexibility, and acceptable performance. However, most existing CLS-based may suffer from performance degradation during frequency ramps. Considering this, an attempt type-3 phase-locked...

We present results for an heterodyne optical phase-lock loop (OPLL), monolithically integrated on InP with external phase detector and loop filter, which phase locks the integrated laser to an external source, for offset frequencies tuneable between 0.6 GHz and 6.1 GHz. The integrated semiconductor laser emits at 1553 nm with 1.1 MHz linewidth, while the external laser has a linewidth less than...

Analog Delay Line, " has been reviewed in final form. Permission, as indicated by the signatures and dates given below, is now granted to submit final copies to the College of Graduate Studies for approval. ABSTRACT High-speed synchronous interface circuits require that the controlling clock signals be accurately aligned. A dynamic de-skew circuit can be used to ensure good clock alignment acro...

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of the reference clock, according to the workload of the EISC processor. The proposed self-calibration method and a phase detector with an auxiliary cha...

We investigate laser high-order harmonic generation in the presence of interfering light. A relatively weak interfering pulse intersects the primary harmonic-generating laser pulse at the focus. The influence on the harmonic-generation process is studied at near-counterpropagating and at perpendicular angles. The interfering beam creates a standing intensity and phase modulation, which disrupts...

The performance of a coherent delay-locked tracking scheme for direct-sequence/spread-spectrum systems using half-sine or triangular chip waveforms for early and late despreading sequences is analyzed. The effect of band-limiting on the received signals is considered. Mean time to lose lock (MTLL) and root mean square (rms) tracking error of the delay-locked loop (DLL) are compared with that of...