This paper presents high speed digital Finite Impulse Response (FIR) filter relying on Wallace tree multiplier and Carry Select Adder (CSLA). Adder has three architectures such as basic CSLA using RCA (Ripple Carry Adder), CSLA using BEC (Binary to Excess-1 Converter) and CSLA using D-latch. In this paper we propose 4tap FIR Filter architecture using 16-bit CSLA using D-latch and 8-bit Wallace ...

Full adder is the functional building block and basic component in several architectures found in VLSI and DSP applications, Adder is a versatile component and mainly used in addition and multiplication as the basic processing element; Adder in a VLSI application is used in ALU design, Address generation in processors, Multipliers and so on. In DSP applications it is used code for conversion, S...

In this paper propose a new high performance 1 bit full adder cell using XOR/XNOR gate design style as well as lower power consumption. Simulation results illustrate the superiority of the resulting proposed adder against conventional 1-bit full-adder in terms of power consumption improvement performance (98% of 10T, 47% of 14T & 16T), propagation delay and PDP. We have performed simulations us...

Under ideal conditions, Reversible logic gates produce zero power dissipation. So these can be used for low power VLSI design. This paper proposes a new reversible parallel adder/subtractor using 4*4 Reversible DKG gate that can work singly as a reversible full adder and a full subtractor. A serial adder/subtractor is also designed in this paper using Reversible Universal Shift registers and DK...

This paper presents Fault Tolerant Carry Select Adder (FT-CSA), most widely used type of adder, based on the self checking scheme with modular architecture. The error recovery capability is derived using generic input/output combination of carry select adder with predetermined fault and error set. The experimental results show that proposed FT-CSA has nearly 50% overhead compared with the typic...

The method of Logical Effort is an easy way to estimate the delay in a CMOS circuit. In this work application of Logical Effort on transistor level analysis of 32-bit heterogeneous adder architecture is designed and presented. Heterogeneous architecture consists of concatenation of four different sub adders (Ripple Carry, Carry Look Ahead, Carry Skip and Carry Select Adder) to design an adder u...

Single-Electron-Technology (SET) is one of the future technologies distinguished by its small and low power devices. SET also provides simple and elegant solutions for threshold logic gates (TLG’s). This paper presents the design of an optimal TLG adder implemented in SET. It provides a detailed procedure for designing capacitive– input SET TLG’s for building the adder. The paper also presents ...

The VLSI binary adder is the basic building block in any computation unit. It is widely used in the arithmetic logic unit, memory addressing computation and in many other places. In this paper the binary adder is presented with keeping in mind speed, power and finally area. In this paper the BCD adder is designed using the mixed approach such as hierarchical, muxing and variable grouping techni...

Single-Electron-Technology (SET) is one of the future technologies distinguished by its small and low power devices. SET also provides simple and elegant solutions for threshold logic gates (TLG’s). This paper presents the design of an optimal TLG adder implemented in SET. It provides a detailed procedure for designing capacitive– input SET TLG’s for building the adder. The paper also presents ...

-The saying goes that if you can count, you can control. Addition is a fundamental operation for any digital system, digital signal processing or a control system. A fast and accurate operation of a digital system is greatly influenced by the performance of resident adders. In this regard, an efficient hybrid adder that combines a carry select adder and a ripple carry adder using QCA technology...