نتایج جستجو برای: switching logic

تعداد نتایج: 220750  

Journal: :IEEE Trans. on CAD of Integrated Circuits and Systems 1998
José C. Monteiro Srinivas Devadas Abhijit Ghosh

Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a logic circuit, thereby reducing switching activity and power dissipation, without changing logic functionality. In sequential precomputation, output values required in a particular clock cycle are selectively precomputed one clock cycle earlier, and the original logic circuit is “turned...

2011
Nader Noori Laurent Itti

Mental tasks that feature algorithmic processing with symbolic items are shown to rely on brain regions known for visualspatial functions. Yet, exactly how these functions may help execution of amodal tasks remains an open question. Here we propose a hypothesis for manipulation of items in working memory, which relies on registering items in a spatiallyorganized short-term memory store. Switchi...

Journal: :IEEE Trans. Computers 1972
Sudhakar M. Reddy

A technique to design fault-locatable combinational switching circuits is given. The networks resulting from the application of the proposed technique have at most three levels of gates.

Journal: :IEEE Trans. on CAD of Integrated Circuits and Systems 1994
Chi-Ying Tsui Massoud Pedram Alvin M. Despain

We propose a new power consumption model which accounts for the power consumption at the internal nodes of a cmos gate. Next, we address the problem of minimizing the average power consumption during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the rst step, we generate a nand decomposition of an optimized Boolean network such that the sum of average...

1997
M. Noroozian G. Andersson K. Tomsovic

This paper presents a fuzzy logic controller for series reactance switching to damp power system electromechanical oscillations. A set of control rules are constructed and inference is provided by fuzzy logic reasoning. The knowledge base for the controller is established from observation of the dynamicrd behaviour of a simple power system and the general engineering knowledge about the system ...

2006
Xiao Yan Yu Robert K. Montoye Kevin J. Nowka Bart R. Zeydel Vojin G. Oklobdzija

Introduction of sub-90nm technology has made a profound impact on circuit designs. Thus, it requires understanding of existing design styles for desired energy-efficiency. We compare adder designs in the energy-delay space, implemented with Limited Switch Dynamic Logic (LSDL) and Compound Domino Logic (CD) in a 65nm SOI technology. Evaluation results show that LSDL can provide more than 35% ene...

2011
D. M. Miller

This paper presents a method of constructing the switching function using edge-valued decision diagrams. The proposed method is as following. The edge-valued decision diagram is a new data structure type of decision diagram which is recently used in constructing the digital logic systems based on the graph theory. Next, we apply edge-valued decision diagram to function minimization of digital l...

2009
Alan Mishchenko Robert Brayton Stephen Jang Kevin Chung

The paper describes several complementary algorithms for power-aware logic optimization: o SimSwitch is an efficient sequential simulator for estimating switching activity of signals in large sequential designs. o PowerMap uses switching activity to make better decisions during power-aware technology mapping. o PowerDC is a resynthesis algorithm that eliminates wires with high switching activit...

Journal: :J. Inform. and Commun. Convergence Engineering 2010
Chun-Myoung Park

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous ...

2004
Rajendra V. Boppana

Recent multiprocessors such as Cray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic qnd switching hardware is partitioned into multiple modules, with each module suitable for implementation as a chip. This paper proposes a method to incorporate adaptivity into such routers with simple changes to the router str...

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