Due to the significant contribution of interconnect to the area and speed of today’s circuits and the technological trend toward smaller and faster gates which will make the effects of interconnect even more substantial, interconnect optimization must be performed during all phases of the design. The premise of this paper is that by increasing the interaction between logic synthesis and physica...

Process technology advances have made multimillion gate field programmable gate arrays (FPGAs) a reality. A key issue that needs to be solved in order for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures. Channel segmentation designs have been studied to some degree in much of the literature; the previous methods are based on experimen...

Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects routability, performance, heat distribution, and to a less extent, power consumption of a design. Traditionally, it is applied after the logic synthesis stage and before the routing stage. Since the advent of deep submicron process techn...

We study treewidth sparsifiers. Informally, given a graph G of treewidth k, a treewidth sparsifier H is a minor of G, whose treewidth is close to k, |V (H)| is small, and the maximum vertex degree in H is bounded. Treewidth sparsifiers of degree 3 are of particular interest, as routing on node-disjoint paths, and computing minors seems easier in sub-cubic graphs than in general graphs. In this ...

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This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (...

In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacity constraints as well as achieving higher routability and good routing flexibility. The init i a l solution consists of nets routed independently b y the SERT-C algorithm which minimizes the Elmore delay at critical si...

compute chip: Synthesis, timing, and physical design A. A. Bright R. A. Haring M. B. Dombrowa M. Ohmacht D. Hoenicke S. Singh J. A. Marcella R. F. Lembach S. M. Douskey M. R. Ellavsky C. G. Zoellin A. Gara As one of the most highly integrated system-on-a-chip application-specific integrated circuits (ASICs) to date, the Blue Genet/L compute chip presented unique challenges that required extensi...

Contemporary field-programmable gate arrays (FPGAs) are predestined for the application of finite impulse response (FIR) filters. Their embedded digital signal processing (DSP) blocks for multiply-accumulate operations enable efficient fixed-point computations, in cases where the filter structure is accurately mapped to the dedicated hardware architecture. This brief presents a generic systolic...

In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells and allocated as “whitespace.” This is done for a variety of reasons including the need for subsequent buffer insertion, as a means to ensure routability, signal integrity, and low coupling capacitance between wires, and to improve yield through DFM optimizations. To this end, layout ...