In this paper, we describe the applicability and efficiency of several power reduction techniques applied on a modern 65nm FPGA. For the given algorithm, image erosion and dilation, two major solutions were tested and compared with respect to power and energy consumption. Firstly the algorithm was run on a general purpose processor (gpp) NIOS and then hardware architecture of an Intellectual Pr...

Contemporary digital hearing aids typically provide substantial benefit to children with mild to moderately severe hearing loss. However, for many hearing-impaired children, difficulty remains with certain aspects of speech recognition and production, such as the phonemes /s/ and /z/. The Phonak Nios micro-hearing aid utilises non-linear frequency compression (NLFC) technology, designed to lowe...

In this paper, we show a very efficient side channel attack against HMAC. Our attack assumes the presence of a side channel that reveals the Hamming distance of some registers. After a profiling phase in which the adversary has access to a device and can configure it, the attack recovers the secret key by monitoring a single execution of HMAC-SHA-1. The secret key can be recovered using a "temp...

In the last ten years, interval techniques [1, 2] have allowed original solutions for many problems in engineering to be proposed, see, e.g., [3]. One of the main features of interval techniques is their ability to provide guaranteed results, i.e., with a verified accuracy or which are numerically proved. Consider for example, a bounded-error parameter estimation problem: the value of some para...

This paper presents a case study of a hardware-software codesign of the RSA cipher embedded in reconfigurable hardware. The 16 and 32-bit soft cores of Altera’s Nios RISC processor are used as the basic building block of the proposed complete embedded solutions. The effect of moving computationally intensive parts of RSA into an optimized parameterized scalable Montgomery coprocessor(s) is anal...

-This paper presents a novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. The proposed test pattern generator reduces the switching activity among the test patterns at the most. In this approach, the single input change patte...