The need for detailed simulation of integrated circuits has received significant attention since the early stages of design automation. Given the increasing device integration, these simulations have extreme memory footprints, especially within unified memory hierarchies. This paper overcomes the infeasible memory demands of modern circuit simulators. Structural partitioning of the netlist and ...

This paper demonstrates the use of quasi-floating gate MOSFET (QFGMOS) in the design of a current-to-voltage converter that operates for the input current range of 0 to 50?A. The workability of the circuit has been verified using SPICE simulations for 0. 18?m CMOS technology with the supply voltages of ±0. 5V. From the simulation results, it has been observed that the proposed circuit has low p...

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS tec...

This paper presents a methodology that addresses short-channel effects to design MOSFET circuits. The circuit design is based on a combination of parameter extraction and simple analytical models that allows precise results. The extraction mainly depends on the inversion level, which is independent of geometry, therefore providing points that are applicable to a wide variety of circuits. Trade-...

This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling Σ∆ A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1V) low-power (below 100μW) all-MOS basic building blocks is proposed. The resulting ana...

1.1 CMOS downscaling to DG-MOSFETs As device scaling aggressively continues down to sub-32nm scale, MOSFETs built on Silicon on Insulator (SOI) substrates with ultra-thin channels and precisely engineered source/drain contacts are required to replace conventional bulk devices (Celler & Cristoloveanu, 2009). Such SOI MOSFETs are built on top of an insulation (SiO2) layer, reducing the coupling c...

1.1 CMOS downscaling to DG-MOSFETs As device scaling aggressively continues down to sub-32nm scale, MOSFETs built on Silicon on Insulator (SOI) substrates with ultra-thin channels and precisely engineered source/drain contacts are required to replace conventional bulk devices (Celler & Cristoloveanu, 2009). Such SOI MOSFETs are built on top of an insulation (SiO2) layer, reducing the coupling c...

The Balanced Differential Amplifiers play a most important role as basic building block in instrumentation amplifier circuit. One of the characteristic of a differential amplifier, the common mode rejection ratio (CMRR) is most important. The active load used for balanced differential amplifier is going to affect differential gain, thus CMRR of the circuit. The active load used can be a diode c...

This paper introduces a software support tool for an advanced electronics laboratory session on circuit synthesis. The application provides the students with a handy tool for structural synthesis of translinear circuits. For a given arbitrary function the program yields a set of realizations, with BJT or MOSFET, which are automatically compared by SPICE simulation, considering the criteria: sta...

ABSTRACT : A circuit design for a low-power full adder array-based multiplier in domino logic is proposed. It is based on Wallace tree technique. Clocked architecture results in lower power dissipation and improvements in power-delay product. The proposed technique is general and can be used in all domino logic circuit designs. Higher order multipliers like 16x16, 32x32 may also be implemented ...