The efficiency of cell-based design synthesis of high performance circuit is strongly dependent on the content of the library. Great effort has been given in the design of libraries, to define the optimal selection of the logic gate drive strength. But few justifications are available to determine the P/N width ratio of each cell. In this paper we use an extension of the logical effort model to...

For digital circuits with ultra-low power consumption, floating-gate circuits have been considered to be a technique potentially better than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper the basic performance related properti...

I. ABSTRACT (SESSION 2) A. Statistical Gate Delay Static Timing Analysis (STA) tools are widely used for efficient timing checks on large chips. In early times, the nonlinear delay model (NLDM) was widely used for STA. As technology downscaled into ultra-deep sub-micron region, noise and coupling considerations require advanced gate mod-eling for STA. Croix and Wong proposed a current source dr...

this article proposes a direct method for solving three types of integral equations with time delay. by using operational matrix of integration, integral equations can be reduced to a linear lower triangular system which can be directly solved by forward substitution. numerical examples shows that the proposed scheme have a suitable degree of accuracy.

DC and intrinsic low-frequency noise properties of p-channel depletion-mode carbon nanotube field effect transistors (CNT-FETs) are investigated. To characterize the intrinsic noise properties, a thin atomic layer deposited (ALD) HfO(2) gate dielectric is used as a passivation layer to isolate CNT-FETs from environmental factors. The ALD HfO(2) gate dielectric in these high-performance top-gate...

A new probabilistic method to estimate the switching activity of a logic circuit under a real delay gate model, is introduced. Based on Markov stochastic processes and generalizing the basic concepts of zero delay-based methods, a new probabilistic model to estimate accurately the power consumption, is developed. More specifically, a set of new formulas, which describe the temporal and spatial ...

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2 inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of t...

Two high-resolution time-interval measuring systems implemented in a SRAM-based FPGA device are presented. The two methods ought to be used for time interpolation within the system clock cycle. We designed and built a PCB hosting a Virtex-5 Xilinx FPGA. We exploited high stability oscillators to test the two different architectures. In the first method, dedicated carry lines are used to perform...

Impacts of source/drain (S/D) recess engineering on the device performance both gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that off-leakage, including subthreshold leakage through channel (Isub) punch-through (IPT) in sub-channel, is strongly related to S/D process. Firstly...

This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented algorithm is complete in the sense that if a delay test exists it will generate an optimal delay test. An optimal delay test for a gate delay fault is a test that sensitizes the longest functional path through the fault site. Es...