ro determine whether an integrated digital circuit is working properly, one may apply to the circuit a set of· well-devised test sequences and compare the resultant outputs with the corresponding correct outputs. Any discrepancies indicate the presence of a fault. The main task here is to find a set of test sequences which can detect the presence of any prescribed fault in the circuit. This tes...

Circuit design in deep sub-micron technologies requires that designers deal with numerous data, constraints, analysis, synthesis, and optimization tools. Although synthesis tools are widely used at Intel, new circuit technologies are evolving and are often not well supported by existing synthesis tools. Deep sub-micron technology requires that the impact of physical design be considered early i...

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circ...

The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic enc...

As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltages well under 1 V. Although dramatic power reductions can be achieved using low supply voltages in high performance applications, the increased subthreshold leakage that results when transistor threshold voltages are l...

Correct operation of synchronous digital circuits requires propagation delays of all sensitizable paths in the circuit to be smaller than a speciied limit. Physical defects and processing variations in integrated circuits can aaect the temporal behavior of a circuit without altering the logical behavior. These defects are called delay faults. In order to design, and especially to synthesize, hi...

Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor leveI and .lhis technique is based on analyzing the off-set of the function during off-line testing.

Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurability, or even be used for post -fabrication modifications. Also, by catering the logic to the SoC domain, additional area/delay/power gains can be achieved over current, more general reconfigurable fabrics. This paper ...

We describe an approach to estimate the average power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit power es...