OVERVIEW: The introduction of low-k and ultralow-k dielectric films in copper-interconnect structures presents serious challenges in test, assembly, and packaging of advanced devices. Low-k films support higher circuit speeds and enable smaller feature sizes by increasing the insulation capability around copper interconnects, but compared to previous generations of silicon-dioxide dielectric la...

Intralevel Time Dependent Dielectric Breakdown (TDDB) was studied in interdigitated comb structures comprised of standard Cu metallization and a low-k interlevel dielectric. The failure distribution was found to be best represented as being lognormal with sigma increasing as the field decreased. Kinetic studies revealed an exponential dependence on the electric field that fits 1/E closer than –...

Recently, very promising properties of epitaxially grown, crystalline rare-earth metal-oxides have been reported [1] and the integration of Pr2O3 dielectric in a conventional polysilicon CMOS process was successfully demonstrated [2]. However, high temperature annealing [3] and aggressive reactive ion etching (RIE) was found to degrade the initial quality of the sensitive high-K gate stack [2]....

In this paper, RF MEMS Capacitive Switches for two different dielectrics hafnium oxide (HfO2) and silicon nitride (Si3N4) are presented. The switches have been characterized and compared in terms of RF performance. The major impact of the change from Si3N4 to HfO2 having dielectric constant 20 is the reduction in overall dimension of the switch; capacitive area is reduced by 66% leading to over...

The capacitance and leakage current properties of multilayer La2O3/Al2O3 dielectric stacks and LaAlO3 dielectric film are investigated in this paper. A clear promotion of capacitance properties is observed for multilayer La2O3/Al2O3 stacks after post-deposition annealing (PDA) at 800 °C compared with PDA at 600 °C, which indicated the recombination of defects and dangling bonds performs better ...

We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p-and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45nm high-performance logic technology node. 1. Introduction The silicon industry has been scaling SiO2 aggressively for the past 15 years for low-power,...

High-performance inversion-type enhancement-mode nchannel MOSFETs on In-rich In0.75Ga0.25As using ALD Al2O3 as high-k gate dielectrics are demonstrated. The maximum drain current, peak transconductance, and the effective electron velocity of 1.0 A/mm, 0.43 S/mm and 1.0x10 cm/s at drain voltage of 2.0 V are achieved at 0.75μm gate length devices. The device performance of In-rich InGaAs NMOSFETs...

Non-uniformity of the dielectric properties of highmaterial due to random grain orientation and phase separation will lead to variation in characteristics between different devices. Here we present a model for phase separated highdielectrics and investigate, by means of 3D numerical device simulation, the intrinsic parameter fluctuations which result from this structural non-uniformity.

We consider the problem of unique identification of dielectric coefficients for gratings and sound speeds for wave guides from scattering data. We prove that the “propagating modes” given for all frequencies uniquely determine these coefficients. The gratings may contain conductors as well as dielectrics and the boundaries of the conductors are also determined by the propagating modes.