With the dramatic increase in mask costs, multi-project wafers have became an attractive choice for low-volume chip fabrication. By using the same set of masks to fabricate a number of different chips, the mask-set cost is amortized among different chip providers, leading to significant cost reduction especially for chip prototyping. In this paper we present a new algorithm for reticle floorpla...

High-performance design flows for FPGAs often rely on module generators to counter coarse logic-block granularity and limited routing resources, However, the very flexibility of current generator systems complicates their integration and automatic use in the entire tool flow. As a solution to these problems, we have introduced FLAME, a common model to express generator capabilities and module c...

Module floorplanning/placement considering boundary constraints is practical and crucial in modern designs because designers may want to place some I/O involved modules along the chip boundary to minimize both chip area and off-chip connections. In this paper, a boundary information checking algorithm based on a general structure representation, called Generalized Polish Expression (GPE), is pr...

In this paper, we present an open source partial reconfiguration (PR) system which is designed for portability and usability serving as a reference for engineers and students interested in using the advanced reconfiguration capabilities available in Xilinx FPGAs. This includes design aspects such as floorplanning and interfacing PR modules as well as fast reconfiguration and online management. ...

In this paper, we propose LaySeq a new representation for non-slicing floorplans and show its superior properties. Layseq uses only n[lg n] bits for a floorplan of n rectangular blocks. The solution space size of layseq is just O(n!). This is very smaller than that of all recent representations. Given a layseq it takes only linear time to construct the floorplan. Layseq is very simple and easy ...

CMOS technology has continuously scaled into deep sub-micron regime. With CMOS scaling, many complex design issues arise. The challenges include, but not limited to, the increasing of interconnect delay and power, exponential growth of leakage power, and rapid growth of design complexity. These challenges motivate us to design new CAD algorithms to reduce power consumption (both leakage power a...

The design process for VLSI systems requires several iterations of the physical design cycle. After a partitioning of the circuit and a floorplanning step, the circuit components are placed. The wires between the components are then routed taking the placement into account. A bad placement cannot be solved by a good routing. Therefore, the information obtained during routing generally leads to ...

The development of integration technology has followed the famous Moores Law, which was stated by Gordon Moore in the year 1965, that “the number of transistors per chip would grow exponentially (double every 18 months)”. In fact, the doubling period has even shortened to a mere 12 months. Field programmable gate arrays (FPGAs) have been popular for more than 20 years, and the market size has b...