نتایج جستجو برای: delay locked loop
تعداد نتایج: 269099 فیلتر نتایج به سال:
طراحی PLL دو حلقه ای مبتنی بر آشکارسازی فاز پنجرهای با سرعت قفل بالا، توان مصرفی و اسپور مرجع پایین
In this paper, a dual loop PLL with short locking time, low power consumption and low reference spur is presented. The output frequency and reference frequency of the designed circuit are 3.2 GHz and 50 MHz, respectively, aimed to WiMAX applications. In the proposed circuit in locked state, some parts of the circuit could be powered off, to reduce overall power consumption. Phase detection in t...
With the development of designing and manufacturing level for micro-electromechanical system (MEMS) gyroscopes, control circuit has become a key point to determine their internal performance. Nevertheless, phase delay electronic components may result in some serious hazards. This study described real-time correction MEMS vibratory gyroscopes. A detailed theoretical analysis was provided clarify...
In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concer...
This survey is devoted to the dynamic analysis of the Costas loop. In particular the acquisition process is analyzed in great detail. Acquision is most conventiently described by a number of frequency and time parameters such as lock-in range, lock-in time, pull-in range, pull-in time, and hold-in range. While for the classical PLL equations for all these parameters have been derived (many of t...
Carrier tracking algorithm based on joint acquisition of frequency locked loop and phase locked loop
In this paper a new method is introduced and investigated for removing the destabilizing effects of time-delay parameter in control loops. The concept of the method is taken from the knowledge concerning the dynamic behaviour of irrational transfer functions (Ir-TF), which is discussed and investigated elswhere in frequency response domain and is explained briefly here. Ir-TFs, which are we...
flip-flop circuit technique has been designed. CMOS new flip-flop circuit with CMOS domino logic which, All the flip-flops were designed using UMC 180. Recognize standard circuit symbols for D Type flip-flops. though can be largely prevented by using the Edge Triggered D Type flipflop illustrated in Fig 5.3.3. locked loop, using 32 nm CMOS technology. Here we design D flipflop for Phase locked ...
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