Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full ad...

Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture beco...

In this project, we had proposed architecture for high speed Truncation Adder Algorithm. In modern VLSI technology, the occurrence of all kinds of errors has always to be expected. By adopting and introducing a novel error–tolerant adder in VLSI design. This error-tolerant adder is easy to develop the accuracy out puts and at the same time it achieves tremendous improvements in both the power c...

The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses “flagged prefix addition” to merge rounding with the significand addition. The floating-point adder is implemented in 0:5 m CMOS, measures 1:8mm2, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-...

[email protected] 1 , [email protected] 2 , Abstract—the most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved. Addition is a fundamental arithmetic operation and it is the base for arithmetic operations such as multiplication and the basic adder cell can be modified to function as subtractor by adding ano...

A new proposal is given to design a spin half-adder in nano-junction. It well known that at finite voltage net circulating current (known as circular current) appears within mesoscopic ring under asymmetric ring-to-electrode interface configuration. This induces magnetic field the center of ring. We utilize this phenomenon construct half adder. The induced used regulate alignments local free sp...

BACKGROUND Death adders (Acanthophis spp) are found in Australia, Papua New Guinea and parts of eastern Indonesia. This study aimed to investigate the clinical syndrome of death adder envenoming and response to antivenom treatment. METHODOLOGY/PRINCIPAL FINDINGS Definite death adder bites were recruited from the Australian Snakebite Project (ASP) as defined by expert identification or detecti...

In this paper we present a 1 bit Full Adder Cell. It was implemented with lesser number of transistors and lesser power consumption compared to the existing implementations of the Full Adder. Simulations are carried for supply voltages of 1.2v, 0.8v in HSPICE at 0.18μmCMOS technology. Proposed Full Adder results show that there was a reduction of power consumption and efficient in area. Area wa...

We present an arithmetic circuit performing constant modular addition having $O(n)$ depth of Toffoli gates and using a total $n+3$ qubits. This is improvement by factor two compared to the width state-of-the-art Toffoli-based adder. The advantage our adder, ones operating in Fourier basis, that it does not require small-angle rotations their $\text{Clifford}+T$ decomposition. Our uses recursive...

This study examines how different initial design decisions affect the area, timing, and power of technology-mapped designs. ASIC flow, tools used during factors to consider maximize performance ratio are discussed. The ALU (Arithmetic Logic Unit) is a fundamental part all processors. In this study, two ALUs were implemented using types adder circuits: Ripple Carry Adder (RCA) Sklansky adder. Ca...