When designing a VLSI circuits, most of the efforts are now performed at levels of abstractions higher than gate. Correspondingly to this clear trend, there is a growing request to tackle safety-critical issues directly at the RT-level. This paper presents a complete environment for considering safety issues at the RT level. The environment was implemented and tested by an industry for devising...

We analyze the latency of fault-tolerant quantum computing based on the 9-qubit Bacon-Shor code using a local, two-dimensional architecture. We embed the data qubits in a 7 by 7 array of physical qubits, where the extra qubits are used for ancilla preparation and qubit transportation by means of a SWAP chain. The latency is reduced with respect to a similar implementation using Steane’s 7-qubit...

We present a Built-In Self-Test (BIST)-based diagnostic approach for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) that can be used for either on-line or off-line testing. The technique was originally intended for on-line diagnosis of faulty interconnect to support fault-tolerant applications. However, the technique has been proven to be an excellent approach...

As a design study for the LHC experiments a 'Low Noise Amplifier Shaper' for capacitive detectors is developed. This amplifier is designed in 0.6 um CMOS technology from AMS. The goal was to design an amplifier with a noise contribution of 250 electrons, and 12 electrons per pF contribution from the input capacitor and a relative high gain. A test chip with two versions of the amplifier, a 'rad...

We propose a scheme to realize scalable quantum computation in a planar ion crystal confined by a Paul trap. We show that the inevitable in-plane micromotion affects the gate design via three separate effects: renormalization of the equilibrium positions, coupling to the transverse motional modes, and amplitude modulation in the addressing beam. We demonstrate that all of these effects can be t...

As transistor geometries are reduced, quantum effects begin to dominate device performance. At some point, transistors cease to have the properties that make them useful computational components. New computing elements must be developed in order to keep pace with Moore’s Law. Quantum dot cellular automata (QCA) represent an alternative paradigm to transistor-based logic. QCA architectures that ...

We describe in detail a general strategy for implementing a conditional geometric phase between two spins. Combined with single-spin operations, this simple operation is a universal gate for quantum computation, in that any unitary transformation can be implemented with arbitrary precision using only single-spin operations and conditional phase shifts. Thus quantum geometrical phases can form t...

I discuss how to perform fault-tolerant quantum computation with concatenated codes using local gates in small numbers of dimensions. I show that a threshold result still exists in three, two, or one dimensions when next-to-nearest-neighbor gates are available, and present explicit constructions. In two or three dimensions, I also show how nearestneighbor gates can give a threshold result. In a...

We implement all single-qubit operations with fidelities significantly above the minimum threshold required for fault-tolerant quantum computing, using a trapped-ion qubit stored in hyperfine "atomic clock" states of ^{43}Ca^{+}. We measure a combined qubit state preparation and single-shot readout fidelity of 99.93%, a memory coherence time of T_{2}^{*}=50  sec, and an average single-qubit gat...

Abstract: In this paper the design of a high voltage tolerant and reliable CMOS I/O buffer is proposed without using thick-oxide devices. In this presented design for mixed low voltage interface applications, it uses a simpler structure and therefore the circuit has good gate-oxide reliability. In addition, it is free of dc leakage current. No additional pad for dual power supplies is required ...