A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold (<Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μ...

This study was undertaken to determine the susceptibility of the Texas Instruments TLK2711-SP Class V Transceiver to single event upsets caused by heavy ion irradiation. The device was tested both in a self-test mode and while actively communicating with a Bit Error Ratio Tester (BERT) during irradiation. Data was recorded to determine the bit error ratio (BER) resulting from a heavy ion enviro...

ata recorders make it possible for the Near Earth Asteroid Rendezvous (NEAR) spacecraft to delay and slow the transmission of information to Earth, thereby accommodating the temporal and bandwidth limitations of the communications link. NEAR is the first spacecraft developed by the Applied Physics Laboratory to employ solid-state recorders, supplanting magnetic tape recorders used previously. A...

www.xilinx.com 1 © Copyright 2012–2015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Occasionally, electronic devices exhibit erroneous behavior for no apparent reason. Through ...

www.xilinx.com 1 © 2008–2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. In the September 2005 issue of IEEE Transactions on Device and Materials Reliability, the article entitled The Rosetta Experiment: Atmospheric Soft Error Rate Testing i...

www.xilinx.com 1 © Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Occasionally, electronic devices exhibit erroneous behavior for no apparent reason. Through careful exper...

This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliability of commercial electronics. For the first time, a fast and accurate technique based on static, vector-less analysis of soft error rates (SER) in general combinational circuits is proposed. The analysis technique is...

The benefits of FPGAs over ASICs become ever more compelling as rapid-process technology scaling and innovation provide ever-greater speed, density, and power improvements. However, along with technology scaling come other effects that previously could be ignored. One of the accompanying effects is increased susceptibility to soft errors caused by single event upsets (SEUs). Although through ca...

SRAM-based FPGAs are increasingly becoming more popular in applications where high dependability, low cost, and fast time-tomarket are important constraints. However, these devices are more susceptible to single-event upsets (SEUs) compared ASIC designs. The error models of SRAM-based due to SEUs are more complicated than those of ASICs since soft-errors in the configuration memory result in pe...

Embedded processor cores, which are widely used in SRAM-based FPGA applications, are candidates for SEU (Single Event Upset)-induced faults and need to be tested occasionally during system exploitation. Verifying a processor core is a difficult task, due to its complexity and the lack of user knowledge about the core-implementation details. In user applications, processor cores are normally tes...