Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance...

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Transactions on 1 2 4 8 1 6 New Univ. Wilton Subset Fig.7. Delay desults the Subset switch block. However, this is the average over 19 circuits; in 9 of the 19 circuits, the proposed switch block actually resulted in faster circuits. 5 Conclusions In this paper, we h a ve presented ...

Routability in a standard cell-based physical design flow has emerged as a critical objective in order to meet tight scaling and area requirements while conforming to the increasingly complex design rules. Access to the cell I/O pins can become severely limited based on constraints such as local routing resources, number of tracks, pre-existing nets blocking approach directions, and so on. In t...

Mobile IPv6 (mipv6) is an internet protocol that allows mobile nodes to have continuous network connectivity to the internet without changing their ip addresses while moving to other networks. The packets sent from Correspondent Node (CN) to a Mobile Node (MN) go first through the mobile node’s Home Agent (HA). Then the HA tunnels them to the MN’s foreign network. This process of delivering the...

The North American Electric Reliability Corporation (NERC) envisions a smart grid that aggressively explores advance communication network solutions to facilitate real-time monitoring and dynamic control of the bulk electric power system. At the distribution level, the smart grid integrates renewable generation and energy storage mechanisms to improve the reliability of the grid. Furthermore, d...

Field programmable gate arrays (FPGA ’s) reduce the turnaround time of application-spec@c integrated circuits from weeks to minutes. However, the high complexity of their architectures makes manual mapping of designs time consuming and error prone thereby offsetting any turnaround advantage. Consequently, effective design automation tools are needed to reduce design time. Among the most importa...

| Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is the least understood, however, it models routability most accurately. In this paper, we study the congestion minimization problem during placement. First, we show that a global placement with minimum wirelength has minimum total congestion. We show that minimizing wirelength may (an...

The study of circuit placement in VLSI physical design has been conducted for several decades. As circuit complexity increases, it is non-trivial to place all cells of the circuit within a reasonable time. Many researchers have presented new placement algorithms and tools to address placement issues such as minimization of wire length, routability, and run-time. Our approach is different in tha...

FPGAs combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic ICs. The Actel family of FPGAs exemplifies the rowbased FPGA model. Rows of logic cells interspersed with routing channels have given this family of FPGA devices the flavor of traditional channeled gate arrays or standard cells. However, unlike the conventiona...

One-dimensional homotopic compaction is defined as; In a given routable layout, a layout of minimum width is reachable by operations that can move each module horizontally as a unit, also deform lines maintaining their connections and maintain their routability. This paper exploits the nature of parallelism of this problem and introduces an efficient cellular automata algorithm for homotopic co...