The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other...

Full Adder is the basic building block for various arithmetic circuits such as compressors, multipliers, comparators and so on. 1-bit Full Adder cell is the important and basic block of an arithmetic unit of a system. Hence in order to improve the performance of the digital computer system one must improve the basic 1-bit full adder cell. In this, Full Adder is designed by using Hybrid-CMOS log...

The paper provides real-word wireless measurement data of the intra-vehicular channel for both the 3-11 GHz and the 55-65 GHz frequency band under similar conditions. By spatially averaging channel impulse response (CIR) realizations within a 10×10 grid, we obtain the power-delay profile (PDP). The data measured at 3-11 GHz and 55-65 GHz exhibit significant differences in terms of root mean squ...

PURPOSE Unique features of adolescent cancer patients include cancer types, developmental stages, and psychosocial issues. In this study, we evaluated the relationship between diagnostic delay and survival to improve adolescent cancer care. MATERIALS AND METHODS A total of 592 patients aged 0-18 years with eight common cancers were grouped according to age (adolescents, ≥10 years; children, <...

The integrated optimization of product development process (PDP) is a critical strategy to improve the product development capability. It should be targeted for time, quality, cost, service and environment. Based on review of existing optimizing methods and tools applied in PDP, which are sorted in their optimizing goals, the problems and difficulties of PDP integrated optimization are put forw...

This paper describes the speed of the design is limited by size of the transistors, parasitic capacitance and delay in the critical path. Power consumption and speed are two important but conflicting design aspects; hence a better metric to evaluate circuit performance is power delay product (PDP).The driving capability of a full adder is very important, because, full adders are mostly used in ...

In this paper, field measurements carried out in a suburban SFN network with two synchronized transmitters are reported. It is found that the radio signal coverage of the distributed transmission scheme is distinctly improved when compared to a single transmitter system. The path loss gain and improvement associated to the SFN scheme are obtained as well as the multipath channel parameters incl...

Background: This paper presents an efficient two-dimensional (2-D) finite impulse response (FIR) filter using block processing for two different symmetries. Architectures a general (without symmetry) and symmetrical filters (diagonal quadrantal are implemented. The proposed architectures need fewer multipliers because of the symmetry coefficients. <ns4...

The register element (flip-flop) is a basic building block to design any clocking system, which consists of the clock distribution tree and flip-flops. A large portion of the on chip power is consumed by the clocking system the total power consumption of the clocking system depends on both clocking distribution tree and also the register elements (flip-flops). The power consumption of register ...

Reversible logic is becoming one of the best emerging design approaches for future computation of reversible logic having its more application in low power application. This logic is applied in the quantum computers, optical computing, communication and nanotechnology. In reversible logic approach generates the garbage input/output. In this paper design of proposed reversible logic multiplexer ...