The three classes of defects that can occur during the manufacturing process of an integrated circuit (IC) are bridge defects, break (open circuit) defects, and parametric delay defects (1). This paper is concerned with defects of the second type (i.e., breaks). They are caused by breaks in the conducting material of a circuit layout due to spot defects, either by lithography-related errors (2)...

Technology scale leads to increasing the vulnerability of new integrated logic circuits. The highenergy neutrons (present in terrestrial cosmic radiation) and alpha particles (that originate from impurities in the packagingmaterials) play important role in occurrence of transient faults which are e®ective factor for designing reliable integrated circuits. Thus, a fast and scalable method to obt...

AbstractIn this paper, the use of Simulated Evolution (SimE) Algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection and allocation. Two goodness measures are designed to guide the selection and allocation operations of SimE. Area, power and delay are considered in the optimization of circuits. Results obtained by SimE algorit...

Negative bias temperature instability has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. In this paper, we construct a comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model. We demonstrate how to solve the reaction–diffusion equations in a way ...

As CMOS technology scales down, the design of ESD protection circuits becomes more challenging. There are some disadvantages for the actual power clamp circuit. In this paper, an optimization ESD power clamp circuit is proposed. The new clamp circuit adopts the edge triggering True Single Phase Clocked Logic (TSPCL) D flip-flop to turn on and time delay, it has the advantage of dynamic transmis...

Multi-phase clocking methods are well known and widely used in high-performance integrated circuit design. Such a scheme allows for relaxation of timing constraints among disjoint partitions of the logic circuitry since lower frequency local clocking is required as compared to the system clock frequency at the cost of increased clock distribution network area. The disadvantage is that multiple ...