This work introduces the use of GradedChannel SOI MOSFETs to make analog current mirrors and compare their performance with those made with conventional fully depleted SOI transistors. It is demonstrated that Graded-Channel MOSFETs can provide higher precision current mirror with enhanced output swing. Also lesser modifications of the output characteristics due to the self-heating effect than i...

This paper proposes a 1.5 V 12-b CMOS ratio-independent algorithmic analog-to-digital converter (ADC) based on a capacitor-mismatch insensitive technique. A novel switched-capacitor multiplying digital-to-analog converter (MDAC) with an accurate gain of two is proposed for an algorithmic ADC. The proposed MDAC architecture requires only one opamp in four phases to generate the next residue outp...

--In this paper, we proposed a new dual threshold circuit technique for reduction of subthreshold and static power dissipation. When the scaling down technology the threshold voltage takes place, due to increasing the leakage current. In this method, n-type and ptype transistor are introduced between the pull up and pull down network, the gateof inserting transistors is connected to the respect...

This brief presents a hybrid of voltage- and current-mode line drivers for the turbo controller area network (CAN). The scheme prevents signal attenuation caused by source termination resistors, it enhances power efficiency. On top that, an adaptive amplitude tuning is implemented to mitigate non-linearity closed-loop gain variations against load impedance variations. proposed driver achieves 8...

The DAC101C081 is a 10-bit, single channel, voltage-output digital-to-analog converter (DAC) that operates from a +2.7V to 5.5V supply. The output amplifier allows rail-to-rail output swing and has an 6μsec settling time. The DAC101C081 uses the supply voltage as the reference to provide the widest dynamic output range and typically consumes 132μA while operating at 5.0V. It is available in 6-l...

A class-AB rail-to-rail CMOS buffer amplifier is proposed and fabricated. The main circuit structure includes a bias circuit, a complementary folded-cascode differential input stage, a common-mode rejection ratio (CMRR) enhancement stage, and a class-AB output stage. With the complementary folded-cascode input stage, high input common-mode range (ICMR) and rail-to-rail output are realized. By u...

This paper reports the performance of an epitaxial layer (ETL) based gate modulated (GM-TFET) through 3D Technology Computer Aided Design (TCAD) simulations. The architecture utilizes effects both vertical tunneling and lateral phenomena to improve device performance. Attributes ETL, its thickness (tepi) doping concentration (Nepi) are varied their impact on electrical parameters such as transf...

The DAC081C081 is an 8-bit, single channel, voltage-output digital-to-analog converter (DAC) that operates from a +2.7V to 5.5V supply. The output amplifier allows rail-to-rail output swing and has an 4.5µsec settling time. The DAC081C081 uses the supply voltage as the reference to provide the widest dynamic output range and typically consumes 132µA while operating at 5.0V. It is available in 6...

Abstract: In the paper, the folded-cascode low-noise operational amplifier (LNA) with constant-gm is proposed and analyzed. The channel-length split technique adopted to expand ratio of W/L of the differential pair transistor to improve the performance of LNA for the gain bandwidth product, noise and offset voltage. The channel-length split method is separated differential input transistor into...

This paper presents high speed and low power full adder cells designed with an alternative internal logic structure and Gate Diffusion Input (GDI) logic styles and hybrid CMOS logic style that lead to have a reduced Power Delay Product (PDP). The main design objective for this adder module is not only providing low-power dissipation and high speed but also full-voltage swing. In the first desig...