The bandwidth and performance of optical phase-lock loops (OPLLs) using single-section semiconductor lasers (SCLs) are severely limited by the nonuniform frequency modulation response of the lasers. It is demonstrated that this restriction is eliminated by the sideband locking of a single-section distributed-feedback SCL to a master laser in a heterodyne OPLL, thus enabling a delay-limited loop...

We propose a piezoelectric transducer-(PZT-) based optoelectronic frequency synchronizer to control simultaneously change in the repetition rate, the relative pulse delay, and the phase noise of a passively mode-locked femtosecond Ti:sapphire laser with an intracavity saturable Bragg reflector absorber with respect to an electronic frequency reference. An optoelectronic phase-locked-loop-based ...

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows ...

A Delay-Locked-Loop with a quasi-linear modified differential delay element is presented. By employing body feed technique in the bias circuit of delay cell in the Multi-Controlled-Delay-Line, applicable range for the controlled signal has been widen to under-threshold voltages, also the nonlinearity of the conventional current starved delay element the has been suppress by bias circuit. Moreov...

A highly integrated 40 Gbit/s coherent optical receiver is reported using a Costas loop as a homodyne optical phase locked loop (OPLL). A photonic IC, an electrical IC, and a hybrid loop filter are characterized, and the feedback loop system is fully analyzed to build a stable homodyne OPLL. All components are integrated on a single substrate within the compact size of 10 × 10mm(2), and a 1.1 G...

From the perspective of differential phase delay experienced by two counterpropagating optical fields, self-starting mode-locked fiber laser with a non-linear amplifying loop mirror (NALM) is theoretically studied. Although it generally believed that NALM shows saturable absorption effect on both continuous wave (CW) light and pulses, we find counter-intuitive fact cross-phase modulation (XPM) ...

1. Definition. A PLL is a feedback system that includes a VCO, phase detector, and low pass filter within its loop. Its purpose is to force the VCO to replicate and track the frequency and phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a phase offset between input and output, but when locked, the frequencies mus...

This paper presents a wide range fast lock all-digital deskew buffer using a digital controlled delay line, which achieves low jitter, fast lock, low power consumption and 50% duty cycle correction. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop. A balanced edge combiner to achieve 50% output clock is also pres...

Yong-Bin Kim* Tom Chen** *Microelectronics Division Samsung Electronics Co. San Jose, CA, USA **Department of Electrical Engineering Colorado State Univ. Fort Collins, CO 80523, USA Abstract This paper describes a CMOS variable delay line Delay Locked Loop(DLL) circuit speci cally designed for reducing clock skew on DRAM/Logic merged integrated circuit using 0.6 m CMOS process. A phase detector...