 Conventional PLL design techniques used to implement CMOS GHz range clock recovery circuits typically suffer from significant power supply coupled noise in large integrated systems. This noise worsens the jitter of the PLL and degrades the system Bit-ErrorRate (BER). This paper describes an analog approach which applies fully differential current steering technique throughout the whole PLL sy...

Neuromorphic circuits—electronic circuits emulating the functionality of the brain—have teased us for fifty years with their potential for creating autonomous, intelligent machines that can adaptively interact with uncertain and changing environments. Although there are many stumbling blocks to achieving that vision, a primary problem has been the lack of a small, cheap circuit that can emulate...

In this paper, we show that the temperature-induced performance drop seen in nanoscale CMOS circuitscan be tackled by powering the circuits with adaptively regulated voltage power supplies. Essentially, when temperature rises, the supply voltage will be bumped up to offset otherwise performance degradation. To avoid thermal over-drift as chip temperature exceeds its operation range, a voltage l...

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘...

Recently deep submicron and SiGe (silicongermanium) bipolar CMOS technologies have enhanced the performance of Si-based radio frequency (RF) integrated circuits up to microwave frequencies. The integration of RF MEMS components, such as inductors and capacitors, could further improve the performance of key RF circuit blocks such as voltage controlled oscillators (VCO), low-noise amplifiers, fil...

This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a wide range of operating frequencies. The design uses static CMOS inverters as a building block of the voltage-controlled oscillator and clock buffering. To reduce supply-induced jitter, programmable circuits with opposite sensitivity compensate for the delay variations...

A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-μm silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of –12.5 dBm, input thirdorder intercept point of –5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm x 0.58 mm. Due to...

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier’s negative feedback. Because the voltage swings of t...

This paper will summarize the technology tradeoffs that are involved in the implementation of radio frequency integrated circuits for wireless communications. Radio transceiver circuits have a very broad range of requirements—including noise figure, linearity, gain, phase noise, and power dissipation. The advantages and disadvantages of each of the competing technologies—Si CMOS and bipolar jun...