Coding techniques for storage systems are gaining traction in data center (DC) applications, owing to their data survivability performance, and more recently, to their ability to mitigate traffic congestion. This paper considers stochastic allocation schedules in networks that admit bulk file requests, across three drive blocking models. We consider a block-based code and a stochastic schedulin...

The execution order of a block of computer instructions on a pipelined machine can make a difference in its running time by a factor of two or more. In order to achieve the best possible speed, compilers use heuristic schedulers appropriate to each specific architecture implementation. However, these heuristic schedulers are time-consuming and expensive to build. We present empirical results us...

This paper presents a treegion-based global scheduling technique for wide issue VLIW/EPIC processors. A treegion is a single-entry/multiple-exit global scheduling scope that consists of basic blocks with control-flow forming a tree. We propose a two-phase approach to global scheduling within a treegion scope that enables speculative code motion in the first phase and uses predication of all ins...

The IA-64 architecture is rich with features that enable aggressive exploitation of instruction-level parallelism. Features such as speculation, predication, multiway branches and others provide compilers with new opportunities for the extraction of parallelism in programs. Code scheduling is a central component in any compiler for the IA-64 architecture. This paper describes the implementation...

Instruction scheduling is one of the most important compiler optimizations. An instruction scheduler reorders instructions to improve performance by minimizing pipeline stalls. Traditional approaches to instruction scheduling were based on heuristics. Over the past decade, however, a number of researchers have proposed optimal solutions to instruction scheduling. This dissertation presents the ...

To exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers offunctional units. Instruction fetch rate must also be increased in order to effectively exploit the performance potential of such processors. Block-structured ISAs provide an effective means of increasing the instruction fetch rate. We define an optimization, calle...

In this paper presents the Linear Cryptanalysis on S-DES and Symmetric Block Ciphers Using Hill Cipher Method. As a vehicle of demonstration of this concept, choose simple yet representative block ciphers such as computationally tractable versions of S-DES, for the studies. The attack presented in this paper is applicable to block structure independently of the key scheduling. The attack needs ...