The most fundamental operation of any processor is the addition. For any circuit there are two important parameters that comes into count is high speed and low power consumption. Hence the speed of various modules should be maximized to dominate overall performance. Depending upon these parameters various adders can be invented like Carry Look Ahead Adder(CLA),Carry Skip Adder(CSA) and Ripple C...

Full Adder is the basic building block for various arithmetic circuits such as compressors, multipliers, comparators and so on. 1-bit Full Adder cell is the important and basic block of an arithmetic unit of a system. Hence in order to improve the performance of the digital computer system one must improve the basic 1-bit full adder cell. In this, Full Adder is designed by using Hybrid-CMOS log...

In this paper we have find great applicability in RNS implementation for the Diminished-one modulo 2n+1 Adder using Circular Carry Selection (CCS) circuit. This adder presents a modulo addition of different bit values for n = 8, 12, 16, 24, 32, 48, 64. We are using the Diminished-one criteria using Circular Carry Selection (CCS) technique for the proposed modulo adder. The circuit design of pro...

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Firstly, this paper proposes novel two transistor AND & OR gates. The proposed AND gate has no power supply, thus it can be referred as the Powerless AND gate. Similarly, the proposed two transistor OR gate has no ground and can be referred as Grou...

BCD Adder is the fundamental adder we learn in logic design and any basic electronics lab. Conventional BCD Adder what we generally know is not feasible for higher bits as they require more area and as they have more propagation delay for higher bit extension. For higher level application BCD design we require more efficient basic BCD block. So in this paper we proposed 2 types of BCD adders na...

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based ...

ÐThis paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder accordi...

On this Technical era the excessive velocity and low area of VLSI chip are veryvery crucial elements. Each day quantity of transistors and different active and passive elements are drastically developing on a VLSI chip. All of the processors of the gadgets adders and multipliers are playing an essential position. An adder is a pleasing element for the designing of fast multiplier. Ultimately he...

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and high-performance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circ...

In present work two new designs for single bit full adders have been presented using three transistors XOR gates. Adder having twelve transistors shows power consumption of 1274μW with maximum output delay of 0.2049ns. Power consumption and maximum output delay shows variation [1274 141.77] μW & [0.2049 – 0.4167] ns with varying supply voltage from [3.3 1.8] V. Further, reverse body bias techni...