Partition noise is closely related to reset noise and has been observed in detection nodes of reset transistor architecture in image sensors. This work presents the analysis of partition noise based on an improved technique for estimation of charge distribution in the transistor channel at any given time instant. We incorporate the transistor turn off transients by taking into account both drif...

In this paper the performance of 8-transistor based Full adder is analyzed, evaluated, and compared with that of three different types of Full Adders based on Complementary Pass Transistor XOR Logic gate. Simulation results using nano-scale SPICE parameters are obtained for the above mentioned FAs. It is shown that the performance of the 8-transistor based Full adder in term of power dissipatio...

Leakage power is increasingly gaining importance with technology scaling. Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. Sleep transistor insertion in circuits is an effective application of MTCMOS technology for reducing leakage power. In this paper we present a fine grained approach where each gate in the circuit is provided an independent...

In this paper, a new method of transistor chaining for 1-D automatic leaf cell synthesis is presented. The method allows synthesis of cells suitable for row-based layouts with no restrictions imposed on network topologies/transistor sizes. The novelty of the solution arises from transistor chaining with integrated dynamic transistor folding. We provide the theoretical analysis of transistor fol...

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by N 2 -tra...

Introduction This application note is focused on exploiting the RF design capabilities of HFA3046/3096/3127/3128 transistor arrays. Detailed design procedures, using these transistor arrays, for a matched (800MHz to 2500MHz) high-gain low-noise amplifier and a 10MHz to 600MHz wideband feedback amplifier are described. The HFA3046, HFA3096, HFA3127, HFA3128 transistor arrays are fabricated in a ...

This paper analyzes maximum output power of class E amplifier with arbitrary transistor. It is important to estimate maximum output power of class E amplifier when a specification of transistor is given. In this paper, values of circuit parameters that gives maximum output power for given operating frequency, dc supply voltage, and output capacitance of the transistor are calculated. This paper...

Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding the optimal number of sleep transistors and their placement as well as optimal P/G network grids, wire widths and layers. This paper presents a fake via based sleep transistor P/G network synthesis method, which addre...

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...

In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows to equalize different path delays without influencing the total delay of the circuit. Unfortuna...