Register allocation and instruction scheduling are antagonistic optimizations: Whichever is applied rst, it will impede the other. To solve this problem, we propose dependence-conscious colouring, a register allocation method that takes the dependence graph used by the instruction schedu-ler into consideration. Dependence-conscious colouring consists of two parts: First, the interference graph ...

In the context of the blurring of boundaries between club and theatre, game and theatre, and party and theatre, experiential spectatorship is spilling into the mainstream. This article starts from the recognition of the rapid rise of the experience economy as a turning point in consumer culture towards a specific appeal to the sensory body. The definition of experience in this analysis is key a...

Register allocation is a compiler phase in which the gains can be essential in achieving performance on new architectures exploiting instruction level parallelism. We focus our attention on loops and improve the existing methods by introducing a new kind of graph. We model loop unrolling and register allocation together in a common framework, called the meeting graph. We expect that our results...

We discuss how Delft-FEWS is applied to incorporate real-time sensor data and dynamic modeling to allow Real Time Control (RTC) of three sewer systems in the area of the Hoeksche Waard, the Netherlands. The purpose of this project was to reduce sewerage spilling to the surface water by optimizing the available storage in the sewer systems. In this paper we will present how Delft-FEWS makes use ...

We present an algorithm to schedule basic blocks of vector three-address-instructions. This algorithm is suited for a special class of vector processors containing a buuer (register le) which may be partitioned arbitrarily into vector registers by the user. The algorithm computes the best ratio of vector register spilling to strip mining, taking the vector length and the buuer size into conside...

The interference graph for a procedure in Static Single Assignment (SSA) Form is chordal. Since the k-colorability problem can be solved in polynomial-time for chordal graphs, this result has generated interest in SSA-based heuristics for spilling and coalescing. Since copies can be folded during SSA construction, instances of the coalescing problem under SSA have fewer affinities than traditio...

Sources of vorticity are examined for a laboratory-generated spilling breaking wave. Two cases are studied. For the first case, based on the breaker height, the Reynolds and Froude numbers are 7370 and 2.04, respectively. The breaker is preceded by 1 mm wavelength capillary waves, with the largest amplitude-to-wavelength ratio equal to 0.18. For this case, it is found that the dominant source o...

Modern processors have multiple pipelined functional units and can issue more than one instruction per clock cycle. This puts great pressure on the instruction scheduling phase in a compiler to expose maximum instruction level parallelism. Basic blocks and superblocks are commonly used regions of code in a program for instruction scheduling. Instruction scheduling coupled with register allocati...

Register allocation is a compiler phase in which the gains can be essential in achieving performance on new architec-tures exploiting instruction level parallelism. We focus our attention on loops and improve the existing methods by introducing a new kind of graph. We model loop unrolling and register allocation together in a common framework, called the meeting graph. We expect our results to ...