A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer...

In this paper, we present and analyze yield enhancement designs for wafer scale Cube Connected Cycles (CCC). Improvements in yield can be achieved through silicon area reduction and/or through the incorporation of defect/fault tolerance into the architecture. Consequently, we first propose a new compact layout strategy for CCC. We then present a novel implementation of wafer scale CCC based on ...

Here we report an approach to roll out Li-ion battery components from silicon chips by a continuous and repeatable etch-infiltrate-peel cycle. Vertically aligned silicon nanowires etched from recycled silicon wafers are captured in a polymer matrix that operates as Li(+) gel-electrolyte and electrode separator and peeled off to make multiple battery devices out of a single wafer. Porous, electr...

As feature sizes continue their frantic descent into the sub-0.6 pm region, wafer cleaning is on its way toward becoming a true enabling technology. Ridding wafers of the i r process chemicals is one of the most common steps in fabrication. It’s also, often a dirty one, in terms of picking up contaminants. The heavy metals, alkali metals and light elements, all common to wafer processing, also ...

A free-space silicon one-dimensional photonic bandgap optical filter is designed and fabricated. A two-stage (110) wafer etching process is employed to form the extremely vertical, smooth, and high-aspect-ratio features that are essential for good optical properties. The (111) oriented planes of the wafer form <0.01 degrees off-vertical trenches that make up the Fabry-Perot filter. A simulation...

A highly efficient grating structure for the coupling between standard optical fibers and single-mode waveguides in the silicon-on-insulator platform realized in a CMOS fabrication process is presented. The cost-effective method introduces a backside metal mirror to the grating coupler without need of an extensive wafer-to-wafer bonding. A coupling efficiency of -1.6 dB (around 69%) near the te...

In this study, a new technique of selective microcap bonding for packaging 3-D MEMS (Micro Electro Mechanical Systems) devices is presented. Microcap bonding on a selected area of the host wafer was successfully demonstrated through flip chip and wafer level alignment. A passivation treatment was developed to separate the microcap from the carrier wafer. A thick metal nickel (Ni) microcap was f...

Metal Deposition or metallization process is one of the processes in fabricating a wafer. A wafer is a thin slice of semiconductor material, such as a silicon crystal, used in the fabrication of integrated circuits and other micro-devices. Due to the nature on the process, it creates lot of particles, which would impact the next process if it were not removed. Particle deposition on the wafer s...

0142-727X/$ see front matter 2008 Elsevier Inc. A doi:10.1016/j.ijheatfluidflow.2008.08.003 * Corresponding author. Tel.: +1 979 845 4500; fax E-mail address: [email protected] (D. Banerjee Surface temperature fluctuations that occur locally underneath departing bubbles in pool boiling are shown to result in local heat transfer coefficients ranging from 1 to 10 kW/cm. These estimates were repo...

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are ...