To provide security to all pairs of nodes in network mobility (NEMO) while executing the handoff between different technologies, a hybrid cryptosystem with suitable selection mechanism is proposed. All nodes, i.e., Mobile Node (MN), Router (MR), Correspondent (CN) and MN, Home Agent (HA), respectively, are considered. A proper proposed confidentiality Bound Update (BU) during conversation MR, H...

This paper is a follow-up to a study published at DesignCon 2004 which addressed the benefits of hybrid (mixed dielectric) stripline constructions by comparing the near-end crosstalk and insertion loss performance of hybrid stripline constructions to industry standard, homogeneous PCB stackups. The present study extends the analysis by comparing dispersion, far and near-end crosstalk, routing b...

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Due to the increasing complexity of the design interactions between the chip and package, it is necessary to consider them at the same time. In order to simultaneously handle chip and package performances, co-design of chip and package is a widely adopted solution, particularly because the finger/pad locations significantly affect IR-drop of the core and the package routing. In this paper, we d...

With the demand of mobility by users, wireless technologies have become the hotspot developing arena. Internet Engineering Task Force (IETF) working group has developed Mobile IP (MIP) to support node mobility. The concept of node mobility indicates that in spite of the movement of the node, it is still connected to the internet and all data transactions are preserved . Network Mobility (NEMO) ...

In this paper we present a low power scan design method. Nowadays the Boundary Scan (BS) diagnostic access to the circuit input and output cells combined with a scan chain of concatenated internal flip-flops (FF) has become to be a standard. An alternative parallel diagnostic access method called Random Access Scan (RAS) is not used in nowadays ICs because of more difficult routability. In spit...

|As the capacities of eld-programmable gate arrays (FPGAs) grow, they will be used to implement much larger circuits than ever before. These larger circuits often require signiicant amounts of storage. In order to address these storage requirements, FPGAs with large embedded memory arrays are now being developed by several vendors. One of the crucial components of an FPGA with on-chip memory is...

We consider a switch module routing problem for symmetrical-array field-programmable gate arrays (FPGA’s). This problem was first introduced in [21]. They used it to evaluate the routability properties of switch modules which they proposed. Only an approximation algorithm for the problem was proposed by them. We give an optimal algorithm for the problem based on integer linear programming (ILP)...

abstract As devices and lines shrink into the deep submicron range, the propagation delay of signals can be eeectively improved by repowering the signals using intermediate buuers placed within the routing trees. Almost no existing timing driven oorplan-ning and placement approaches consider the option of buuer insertion. As such, they may exclude solutions, particularly early in the design pro...

This paper presents a universal field programmable gate array (FPGA) programmable routing circuit, focusing primarily on a delay optimization. Under the precondition of the routing resource’s flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offs...