As a fundamental image processing block, morphological processing involves intensive computation and contributes significantly to an image processing system overhead. Depending on only spatially local data, several morphological operations can be implemented with parallel hardware to reduce the computation overhead. In this paper, we implement morphological image operations, which include dilat...

Real time multi-channel sliding correlation processing is widely applied in underwater communication system or underwater positioning system. The traditional implementation in FPGA always employs parallel method which reduces the design work, however wastes considerable FPGA resources. This paper described a new kind of SOPC structure which based on AVALON bus, taken NIOS CPU as system controll...

This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. Th...

In this paper, the design and implementation results of a system on a chip (SOC) based speech recognition system as software/hardware co-design is presented. The hidden markov model (HMM) is used for the speech recognition. In order to implement this in SOC, the various tasks required are optimally partitioned between hardware and software. The SOC, housed in Altera FPGA boards , has Nios II so...

Many scientific and engineering applications are data intensive. Their data-flow is often the performance limiting factor. When these applications are implemented on a reconfigurable system, the use of long routing resources usually limits the performance. This paper compares cellular design methods for reconfigurable devices which reduce the need for long paths. Two different approaches are pr...

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to co...

This paper, proposes a novel solution for a stereo vision machine based on the System-on-Programmable-Chip (SoPC) architecture. The SOPC technology provides great convenience for accessing many hardware devices such as DDRII, SSRAM, Flash, etc., by IP reuse. The system hardware is implemented in a single FPGA chip involving a 32-bit Nios II microprocessor, which is a configurable soft IP core i...

Solving a system of linear equations i s a key problem in engineering and science. Matrix factorization is a key component of many methods used to solve such equations. However, the factorization process is very time consuming, so these problems have often been targeted for parallel machines rather than sequential ones. Nevertheless, commercially available supercomputers are expensive and only ...

The rough sets’ theory developed in the eighties of the twentieth century by Prof. Z. Pawlak is an useful tool for data analysis. Therefore a lot of rough sets algorithms were implemented in scientific and commercial tools for data processing. But data processing efficiency problem is arising with increase of the amount of data. Software limitations led to searching the new possibilities. Field...