One of the major limiting factors of the CMOS device, circuit and system simulation in sub 100nm regimes is the statistical variability introduced by the discreteness of charge and granularity of matter. The statistical variability cannot be eliminated by tuning the layout or by tightening fabrication process control. Since the compact models are the key bridge between technology and design, it...

This paper proposes a MOSFET-only, 20pA, 780ppm/oC current reference that consumes 23pW. The ultra-low power circuit exploits subthreshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows low supply voltage sensitivity of 0.58%/V and a load sensitivity of 0.25%/V.

This paper deals with the propagation delay comparison of half adder with different FETs; such as MOSFET, CNTFET, FINFET. Nanotechnology is the promising field which functions at the molecular level to replace the conventional use of classical CMOS. By simulation, the best part is got that CNTFET shows lesser delay for half adder circuit.

Snapback breakdown is the second order effect of avalanche breakdown in a device. Snapback occur when the excess supply voltage and high currents created flow through the device and become unstable. These two breakdowns are used to explain the concept of Vertical Impact Ionization MOSFET (IMOS) in its Equivalent Circuit Model. The equivalent circuit model design consists of MOS transistors that...

This paper presents a 0.6-V MOSFET-only subthreshold-leakage suppressed CMOS fully differential switched-capacitor amplifier with an analog T-switch scheme. The circuit uses substrate-biased MOSFETs in its depletion region as capacitors linearized by a compensation technique. The circuit design of major building blocks is described herein. The experimental results demonstrate the performance of...

A DC-DC step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switchedcapacitor voltage tripler architecture with MOSFET capacitors, which results in an area approximately eight times smaller than using MiM capacitors for the 0.13μm CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitance...

As MOSFET sizes and wire widths become very small in recent years, in uence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present formulas of output waveform at driving point and short-circuit power dissipation for static CMOS logic gates driving a CRC load. By representing the short-circuit curr...

VLSI technology is constantly evolving towards smaller line widths. In this paper analytical modeling for triple material double gate (TMDG) MOSFETs has been presented in the field of VLSI technology. An entire circuit is manufactured in a single piece of silicon. The level of integration of silicon technology as measured in terms of number of devices per IC. This leads to the concept of scalin...