One of the challenging issues for semiconductor circuit design is how to overcome RC delays in the interconnect layers. To reduce the overall dielectric constant, it is important to develop a low-k barrier/etch stop film that can prevent the metal lines, usually made of aluminum, from interacting with other materials in multilevel interconnect schemes. An additional requirement for a barrier/et...

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or ‘high K’ gate oxides such as hafnium oxide and hafnium silicate. Little was know...

Germanium (Ge) has gained great attention not only for future nanoelectronics but back-end of line (BEOL) compatible monolithic three-dimensional (M3D) integration recently. For high performance and low power devices, various high-k oxide/Ge gate stacks including ferroelectric oxides have been investigated. Here, we demonstrate atomic layer deposited (ALD) polycrystalline (p-) HfO <sub xmlns:mm...