The floorplanning problem aims to arrange a set of rectangular modules on a rectangular chip area so as to optimize an appropriate measure of performance. This problem is known to be NP-hard, and is particularly challenging if the chip dimensions are fixed. Fixed-outline floorplanning is becoming increasingly important as a tool to design flows in the hierarchical design of Application Specific...

The concept of improving the timing behavior of a circuit by relocating registers is called retiming and was "rst presented by Leiserson and Saxe. They showed that the problem of determining an equivalent minimum area (total number of registers) circuit is polynomial-time solvable. In this work, we show how this approach can be reapplied in the deep sub-micron domain when area-delay trade-o!s a...

We present a timing driven oorplanning program for general cell layouts. The approach used combines quality of force directed approach with that of constraint graph approach. A oorplan solution is produced in two steps. First a timing and connectivity driven topological arrangement is obtained using a force directed approach. In the second step, the topological arrangement is transformed into a...

In this paper we present a 3-D floorplan representation based on the methodologies of Corner Block List (CBL). Our model is an extension and generalization of the original 2-D CBL and inherits its most crucial advantages including: linear time operations and evaluations, relatively small solution space (<n!3) with complex non-slicing structures, etc. Although like other sequence based represent...

To the best of our knowledge, this is the first algorithm unifying arbitrary rectilinear block packing and soft block packing. Furthermore, this algorithm handles arbitrary convex or concave rectilinear block packing in the most efficient way compared to other sequence pair-based approaches. At the same time, the algorithm can handle rectangle soft block effectively. The concept of non-redundan...

Problems unique to the visualization of complex, partially automated design tasks such as VLSl system design are reviewed, and approaches are described. The design domain used to illustrate the approaches is chip-level “floorplanning,” an iterative-refinement design methodology for VLSl layout, routing, and timing control. The general view structure and control structure are described. Other vi...

Two of the major concerns in 3D stacked technology are heat removal and power density distribution. In our work, we propose a novel 3D thermal-aware floorplanner. Our contributions include: 1. A novel multi-objective formulation to consider the thermal and performance constraints in the optimization approach. 2. Two efficient Multi-Objective Evolutionary Algorithm (MOEA) for the representation ...

We consider off-line task placement onto reconfigurable hardware devices (RHDs), which are increasingly used in embedded systems. The tasks are modelled as three dimensional boxes given by their footprint times execution time which results into a three dimensional orthogonal packing problem. Unlike other approaches, we allow several alternative implementation variants for each task, which enabl...

This paper studies the buffer planning problem for interconnect centric floorplanning. Dead-spaces not held by blocks are the available location for buffer insertion. To make best use of these spaces for buffer requirements, we have to move blocks so that blocks’ room size is adjusted and dead-spaces could be redistributed. In this paper, we introduce a new algorithm to move blocks not only wit...

Defect avoidance methods are likely to play a key role in overcoming the challenge of mask blank defects in EUV lithography. In this work, we propose a novel EUV mask defect avoidance method. It is the first approach that allows exploring all the degrees of freedom available for defect avoidance (pattern shift, rotation and mask floorplanning). We model the defect avoidance problem as a global,...