Delay differential equation model of a NOLM-NALM mode-locked laser is developed that takes into account finite relaxation rate the gain medium and asymmetric beam splitting at entrance nonlinear mirror loop. Asymptotic linear stability analysis continuous wave solutions performed in limit large delay indicates class-B flip instability leading to period doubling cascade development square-wave p...

This paper presents a re-circulating delay-locked loop @LL) with various innovations to improve in-band phase noise suppression. The voltage-controlled oscillator @’CO) and bias circuitry incorporate circuit-level techniques that reduce l/f noise through switched biasing. The phase realignment theory presented in [I] is applied to optimize the VCO so as to maximize the phase noise suppression a...

This paper presents a new circuit topology of a phase-locked loop that can be used for synchronising a singlephase wind turbine generator (WTG) with the low voltage utility grid. The circuit is based on the time-delay digital tanlock loop (TDTL) architecture and was modelled and simulated using Simulink/MATLAB. The results presented demonstrate the ability of the circuit not only to synchronise...

Multipath propagation, multiple access interference and non-line of sight propagation, etc. have impeded the accuracy in mobile data measurements. Multiuser receivers in asynchronous Code Division Multiple Access (CDMA) systems require the knowledge of several parameters such as timing delay between users. In this paper, the problem of time delay estimation for CDMA systems is examined by propo...

Feedback systems are important in applications, for example, optical feedback lasers, phase-locked frequency synthesizers and wave equations with feedback stabilization at the boundary, and the problem regarding sensitivity and robustness of the feedback system with respect to time delays has attracted a lot of attention. In this paper we continue the discussion on sensitivity and robustness of...

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-μm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and currentinjection current-mode logic (CICML) divider. A short-pulsed-reset phase fre...

A novel self-timed communication protocol is based upon phase-modulation of a reference signal. The reference and the data are sent on the same transmission lines and the data can be recovered observing the sequence of events on the same lines. The sender block consists of a reference generator and variable-delay elements, while the receiver includes a delay-locked loop for synchronization and ...

A low-power and high-speed frequency multiplier for a delay-locked loop-based clock generator is proposed to generate a multiplied clock with different range of frequencies. The modified edge combiner consumes low power and achieves a high-speed operation. The proposed frequency multiplier overcomes a deterministic jitter problem by reducing the delay difference between positiveand negative-edg...

Photonic integration is very promising to bring down volume and weight of phased-array beamforming networks. In addition, photonics allows for increased functionality for widebandwidth systems. In this paper we demonstrate the feasibility of phase and amplitude control of a 16-element phased-array antenna with a single InP integrated circuit. The concept and design of an optical phase locked lo...

A monolithically integrated p-i-n r HBT photoreceï er was successfully employed in a de ̈elopment platform for hybrid optical ( ) phase-locked loops OPLLs . Despite loop delay compromises necessary for flexibility in component substitution, this OPLL de ̈elopment platform has demonstrated a hold-in range of 1.558 GHz and possible locking frequencies from 1.00 to 20.75 GHz. Q 1997 John Wiley & Son...