the low noise amplifier is the key part for front-end device of the receiver in the GPS. A 1.8V 0.18um CMOS LNA for GPS applications has been designed. Two kinds of low noise amplifier (LNA) for single-end cascade structure and differential cascade structure respectively are presented in this paper. Cadence software is used to optimize the two circuits. It provides a series of good results in N...

This paper presents a design of the transimpedance amplifier using 0.35μm CMOS technology. In the proposed transimpedance amplifier, feedback resistor RF of conventional transimpedance amplifier has been replaced by NMOS transistor as an active feedback resistor. This circuit operates at 3.3V power supply voltage and for a photocurrent of 0.5μA.The proposed transimpedance amplifier having low n...

this paper proposes a low voltage (±0.55v supply voltage) low power (44.65µw) high common mode rejection ratio (cmrr) differential amplifier (d.a.) with rail to rail input common mode range (icmr), constant transconductance (gm) and enhanced frequency performance. its high performance is obtained using a simple negative averaging method so that it cancels out the common mode input signals at th...

A new circuit technique for voltage gain enhancement in CMOS op amp design suitable for low voltage and high speed operation is presented in this paper. A negative conductance is used to cancel the positive output conductance of an amplifier thereby reducing the total equivalent output conductance and increasing the voltage gain of the amplifier. The negative conductance is derived from the out...

In this paper, power amplifier operating with center frequency of 947.5 MHz, which can be used for the transmitter in beamforming systems, is proposed. The power amplifier implemented provides high power added efficiency (PAE) of 71.967% and low noise figure (NF) as low as 1.525. The linearity of the power amplifier is improved by using square law and cubic law analog predistortion techniques. ...

The design of a fully differential CMOS transconductance amplifier is presented in this paper. This amplifier is to be used in the first stage of a 13-bit pipelined A/D converter, and was designed to meet the necessary specifications at a minimum level of power consumption. The amplifier presented below was based on a two-stage design of a telescopic cascode input stage followed by a common-sou...

In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. This paper presents a design of input stage of Operational Amplifier i.e cascode differential amplifier using a standard 65nm CMOS Technology.A comparison betweem gate-driven, bulk-driven and cascode bulk driven bulk-driven differential amplifier is described. The Results demonstrate t...

This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 μm standard CMOS technology and the experimental results agree well with the theory. key words: time a...

A transimpedance amplifier (TIA) is designed based on the first order wave equation. The feedback resistance is set as the ohJective function for transimpedance. The main feedback amplifier provides transimpedance and a wide band compensation amplifier determines the characteristics of overall TIA. The stability of lhe T lA is not affected due to the open loop nature of compensation. Simulation...