In this paper, two general architectures of Carry Select Adder (CSA) have been introduced for high speed addition. These CSA architectures utilize the hybridized structure of Carry Lookahead Adder (CLA) and Ripple Carry Adder (RCA). In these architectures the critical path delay has been reduced by reducing the number of multiplexer stages. The proposed designs are compared with regular CSA bas...

This paper presents a novel low-power and high-speed 1-bit full-adder, which is designed based on pass transistor and TG logics. The main advantage of this design is low propagation delay and lowpower consumption, which leads to achieving lower PDP than others. Intensive HSPICE simulation shows that the new full-adder consumes around 28.5% less power than 14T adder; moreover its PDPis 30% less ...

Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumpti...

High speed Finite Impulse Response filter (FIR) is designed using the concept of faithfully rounded truncated multiplier and parallel prefix adder. The bit width is also optimized without sacrificing the signal precision. A transposed form of FIR filter is implemented using an improved version of truncated multiplier and parallel prefix adder. Multiplication and addition is frequently required ...

Adiabatic logic is used to minimize the energy loss during operation of the circuit. Using two-phase adiabatic static CMOS logic (2PASCL) the power consumption can be reduced. This paper compares the power consumption of Static Energy Recovery Full Adder(SERF) and the proposed full adder using two phase adiabatic static CMOS logic(2PASCL). The average power consumption of proposed full adder is...

Quantum information provides fundamentally different computational resources than classical information. We prove that there is no unitary protocol able to add unknown quantum states belonging to different Hilbert spaces. This is an inherent restriction of quantum physics that is related to the impossibility of copying an arbitrary quantum state, i.e., the no-cloning theorem. Moreover, we demon...

Five cases of adder bites are presented. The clinical effects and current recommendations for the treatment of adder bites are described based on a review of previously published literature. All adder bites, or snake bites of unknown species, should be observed for a minimum of 2 h. Those with no local swelling may be allowed home with appropriate antitetanus prophylaxis. Patients with local re...

This paper presents a new early output hybrid input encoded asynchronous full adder designed using dual-rail and 1-of-4 delay-insensitive data codes. The proposed full adder when cascaded to form a ripple carry adder (RCA) necessitates the use of a small relative-timing assumption with respect to the internal carries, which is independent of the RCA size. The forward latency of the proposed hyb...

In this paper an extensive study on several adders has been manifested to design VLSI applications. Adder circuits plays a major role to modify or design a multiplier. Imprecise adder is one of the design where used in increasing the performance and power efficiency and approximate adders are for error detection and correction.16T full adders is also used to fast and energy efficient adder. An ...