Since nanoelectronic devices are likely to be defective and error-prone, developing an understanding of circuit reliabilities and critical components will be required. In this paper, probabilistic transfer matrices are used to compare the reliability of a small multiplier circuit when considering both magnetic and molecular QCA implementations. These implementations are considered since the cir...

A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 and Virtex-5 Field Programmable Gate Arrays (FPGAs). The Frame ECC logic facilitates the detection of Single Event Upsets (SEUs) in the FPGA configuration memory. The ICAP provides read and write access to the configura...

When coherent states of the electromagnetic field are used to drive the evolution of a quantum computer, a decoherence results due to the back reaction from the qubits onto the fields. We show how to calculate this effect. No assumptions about the environment are necessary, so this represents a useful model to test the fidelity of quantum error correcting codes. We examine two cases of interest...

We investigate the amount of noise required to turn a universal quantum gate set into one that can be efficiently modelled classically. This question is useful for providing upper bounds on fault tolerant thresholds, and for understanding the nature of the quantum/classical computational transition. We refine some previously known upper bounds using two different strategies. The first one invol...

SLAC National Accelerator Laboratory is developing a next generation H-bridge switch plate [1], a critical component of the SNS High Voltage Converter Modulator [2]. As part of that effort, a new IGBT gate driver has been developed. The drivers are an integral part of the switch plate, which are essential to ensuring fault-tolerant, high-performance operation of the modulator. The redesigned dr...

Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability...

We propose a scheme to construct the controlled-phase (c-phase) gate on distant transmon qutrits hosted in different resonators inter-coupled by a connected transmon qutrit. Different from previous works for entanglement generation and information transfer on two distant qubits in a dispersive regime in the similar systems, our gate is constructed in the resonant regime with one step. The numer...

Addition is one of the fundamental arithmetic operations which are used extensively in many VLSI systems such as microprocessors and application specific DSP architectures. In this paper, the Significance Approximation Error Tolerant Carry Select Adder (SAET-CSLA) is constructed, which is efficient in terms of accuracy, power and area. While considering the elementary structure of an image proc...

It is an oft-cited fact that no quantum code can support a set of fault-tolerant logical gates that is both universal and transversal. This no-go theorem is generally responsible for the interest in alternative universality constructions including magic state distillation. Widely overlooked, however, is the possibility of nontransversal, yet still fault-tolerant, gates that work directly on sma...

Fault-tolerant implementation of quantum gates is one preconditions for realizing computation. The platform Rydberg atoms the most promising candidates achieving We propose to implement a controlled-$Z$ gate on where an amplitude-modulated field employed induce antiblockade. Gate robustness against fluctuations in Rydberg-Rydberg interaction can be largely enhanced by adjusting field. Furthermo...