This paper presents a 30dBm (1W) class-E power amplifier projected in a standard 0.18-μm CMOS technology. The power amplifier (PA) consists in two differentials stages. The main stage employs a cascode class-E RF power amplifier with a self-biasing circuit. The driver stage uses the technique of Injection-Locking to substantially reduce the input power signal, maintaining a high gain. At 2.45 G...

The design of high-accuracy analogue circuits is becoming a difficult task with the scaling down of supply voltages and transistor channel lengths of the current mixed-signal integrated circuits. Most of this kind of circuits require the use of the highestperformance active cell: the operational amplifier (op amp). Designers are continuously working toward tradeoff solutions between gain, input...

This letter describes the use of a power-optimized cascode configuration for obtaining maximum output power at millimeter-wave (mm-wave) frequencies for a two-way combined power amplifier (PA). The PA has been fabricated in a high-speed InP double heterojunction bipolar transistor technology and has a total active emitter area of 68.4 lm2. The experimental results demonstrate a small signal gai...

A new very high performance low voltage cascode current mirror (CM) circuit is proposed in this work. The CM utilizes the low supply voltage and low input resistance characteristics of a cascode CM. In this CM, cascode configuration is used to obtain a wide operating current range and resistance compensation technique is incorporated to increase the operating bandwidth. The peaking in frequency...

Short-Cannel MoS2 Transistors Yi Yang, He Tian, Xing Wu, Tian-Ling Ren, and colleagues demonstrate a photolithography resolution-independent method to realize 10 nm short-channel transistors in article 2100543. By depositing the noble electrode partially on self-oxidized aluminum electrode, channel length is directly defined by ≈10 thickness of oxidization layer, which can provide new opportuni...

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on ...

Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown no...

Adiabatic logic is an implementation of reversible logic in CMOS where the current flow through the circuit is The dual rail toffoli gate is designed using transmission gate. minimum sized XOR gate is implemented at 0.12ìm. solving the problems. Transmission Gate (TG) uses to realize complex logic functions by using a small number It is implemented in Standard CMOS logic (3). Proposed CLA imple...

In this paper, we report record radio frequency (RF) performance of carbon nanotube transistors based on combined use of a self-aligned T-shape gate structure, and well-aligned, high-semiconducting-purity, high-density polyfluorene-sorted semiconducting carbon nanotubes, which were deposited using dose-controlled, floating evaporative self-assembly method. These transistors show outstanding dir...

A novel approach for the fabrication of transistors and circuits based on individual single-crystalline ZnO nanowires synthesized by a low-temperature hydrothermal method is reported. The gate dielectric of these transistors is a self-assembled monolayer that has a thickness of 2 nm and efficiently isolates the ZnO nanowire from the top-gate electrodes. Inverters fabricated on a single ZnO nano...