This paper proposes the new authorizing binding mechanism to reduce the binding latency between the mobile node and the correspondent node during Mobile IPv6 handover procedure. The tradeoff between security and QoS during Mobile IPv6 handover procedure is discussed. In the proposed mechanism, the authorizing binding is performed before actual handover for candidate networks where the mobile no...

Field-Programmable Gate Arrays (FPGAs) are flexible circuits that can be (re)configured by the designer. The efficient use of these circuits requires complex CAD tools. One of the steps of the design process for FPGAs is represented by placement. In this paper we present a genetic algorithm for the FPGA placement problem, in particular for the Atmel FPGA circuits. Because of the limited routing...

This paper outlines an FPGA VLSI design methodology that was used to realize a fully functioning FPGA chip in 130nm CMOS with improved routability and memory robustness. The architectural design space exploration and synthesis capability were enabled by the Verilog-to-Routing CAD tool. The capabilities of this tool were extended to enable bitstream generation and deployment. To validate the arc...

We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eeciently evaluating switch module designs 9]. The second is that of evaluating the routability of global routing paths for a placement on this architecture. Only an approximate algorithm was previously known for this problem. In this paper, we present an optimal ...

A switch block M with W terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most W ) is simultaneously routable through M [2]. In this paper, we present an algorithm to construct N -sided universal switch blocks with W terminals on each side. Each of our universal switch blocks has N2 W switche...

This paper presents an automatic layout design system for analog integrated circuits. It is tailed for analog circuit designers so that they can bring their special knowledge and experience into the synthesis process to create high quality layouts. Designers can write and maintain their own technology and application independent module generators for subcircuits in a module generator environmen...

The VLSI placement problem is to place the objects into fixed die such that there are no overlaps among the objects and some cost metric such as wire length and routability is optimized. For this purpose A new routing method is used called , A Deep sub-wavelength lithography, (using the 193nm lithography to print 45nm, 32nm, and possibly 22nm integrated circuits), is one of the most fundamental...

In modern electronic manufacturing processes, multi-layer Printed Circuit Board (PCB) routing requires connecting more than hundreds of nets with perplexing topology under complex constraints and highly limited resources, so that takes intense effort time human engineers. PCB fanout as a pre-design has been proved to be an ideal technique reduce the complexity by pre-allocating resources pre-ro...

Since 1997 there has been a steady stream of advances for the maximum disjoint paths problem. Achieving tractable results usually required focusing on relaxations such as: (i) to allow some bounded edge congestion in solutions, (ii) only consider unit weight (cardinality) setting, (iii) require fractional routability selected demands (the all-or-nothing flow setting). For general form (no conge...

This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits...