In deep submicrometer integrated circuit design, there is a growing need to quickly and accurately characterize the timing of large circuit blocks. Accurate timing characterization requires making available as much timing information as possible at each step of the design process. Conventional fast characterization methods typically employ topological analysis, which can be inaccurate because o...

During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on implementation constraints that are costly to satisfy. For example, the capacitive load of complementary wires in an integrated circuit may need to be balanced. This article describes a novel side-channel analysis resistan...

The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stage can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses...

Problems facing in design migration from FPGA to standard cells design approach are discussed. Standard cell implementation of a parallel multiplier with bit-sequential input and output, using FPGA design as a prototype is considered. It is shown that careful redesign is required, because of incompatibility of the cell libraries. Also the FPGA design complexities don't present any relation to d...

As transistor feature sizes scale below 100nm, the costs of standard-cell-based application specific integrated circuits (ASICs) are increasing so rapidly that fewer products have sufficient volume to justify the high non-recurring engineering (NRE) costs. Consequently, more designs are relying on fully programmable devices such as field programmable gate arrays (FPGAs). Unfortunately, such ful...

A major aspect of human reasoning involves the use of approximations. Particularly in situations where the decision-making process is under stringent time constraints, decisions are based largely on approximate, qualitative assessments of the situations. Our work is concerned with the application of approximate reasoning to real-time control. Because of the stringent processing speed requiremen...

Preface This report is a summary of the activities in the field of resonant tunneling device circuit design. (GMUD) during the first year of the Microelectronics Advanced Research Initiative projects ANSWERS (Autonomous Nanoelectronic Systems with Extended Replication and Signalling) and LOCOM (Logic Circuits with Reduced Complexity based on Devices with Higher Functionality). As part of the AN...

Experimental demonstrations of quantum annealing with “native” implementation Boolean logic Hamiltonians are reported. As a superconducting integrated circuit, problem Hamiltonian whose set ground states is consistent given truth table implemented for no redundant qubits. examples the table, nand and nor successfully fabricated as an identical circuit. Similarly, native multiplier comprising si...

A low dispersion 2-GHz comparator is an essential part of the latest automated VLSI tester by Teradyne Inc. With each new and faster CMOS logic VLSI microchips, faster and more precise comparators are needed to verify that the static discipline is being met on the many pins of the integrated circuit. As the error in the comparator is lowered, the VLSI production yield is greatly increased becau...

In this paper, we characterize the Energy-Delay performance of logic circuits realized using Single Electron Transistor (SET) devices. As technology scaling progresses, it is getting increasingly challenging to continue reducing energy, especially at low activity factors and low VCC, due to increasing leakage energy dominance. A SET can be viewed as the ultimate transistor operating in the limi...