We describe a methodology to design and optimize Three-dimensional (3D) Tree-based FPGA by introducing a break-point at particular tree level interconnect to optimize the speed, area, and power consumption. The ability of the design flow to decide a horizontal or vertical network break-point based on design specifications is a defining feature of our design methodology. The vertical partitionin...

Dual-rail precharge logic (DPL) is a data hiding countermeasure against side channel attacks (SCA). Many variants of DPL have been introduced in the literature which target ASICs, FPGAs and microcontroller. A common problem which leads to failure of DPL on FPGA is imbalanced routing. FPGA designers have limited control over the FPGA placement and routing tools and therefore symmetrically routin...

In this paper we present a new method of integrating the placement and routing stages in the physical design of channel-based architectures, and present the first implementation of this method: Gambit. Based on a graph coloring representation of the routing problem, we are able to produce circuit placements and detailed routes simultaneously, allowing routing constraints to influence decisions ...

In the era of application convergence, the small handheld battery-powered portable devices are required to multiplex their limited hardware resources between many complex applications. Our first contribution in this paper is a modular and block based configuration architecture for modern FPGAs like Xilinx’s Virtex-4 and Virtex-5 devices, to increase multi-tasking capabilities, power savings and...

The architectural regularity of FPGAs provides an inherent redundancy which can be exploited for fault tolerance and yield enhancement. In this paper we examine the problem of recon guring the placement of a circuit on an FPGA to tolerate a given fault pattern in the array of CLBs. The primary objective of the placement recon guration is to minimize timing degradation. The concept of a slack ne...

We introduce a new hybrid net model for timing-driven analytical placement. This new hybrid net model decreases the average critical path delay obtained after global placement with 14% compared to wire-length-driven analytical placement. The obtained HPWL (Half Perimeter Wire-Length) remains the same. This is a very interesting feature of the hybrid net model. We also introduce a new gradual le...

FPGA platforms have been widely used in many modern digital applications due to their low prototyping cost, short time-to-market and flexibility. Field-programmability of FPGA bitstream has made it as a flexible and easy-to-use platform. However, access to bitstream degraded the security of FPGA IPs because there is no efficient method to authenticate the originality of bitstream by the FPGA pr...

This study treats architecture and implementation of a FPGA accelerator for double-precision floating-point matrix multiplication. The architecture is oriented towards minimising resource utilisation and maximising clock frequency. It employs the block matrix multiplication algorithm which returns the result blocks to the host processor as soon as they are computed. This avoids output buffering...

To date, the best algorithms for performing placement on Field-Programmable Gate Arrays (FPGAs) are based on Simulated Annealing (SA). Unfortunately, these algorithms are not scalable due to the long convergence time of the latter. With an aim towards developing a scalable FPGA placer we present an analytic placement method based on a near-linear net model, called star+ . The star+ model is a v...

Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this alg...