نتایج جستجو برای: floorplanning
تعداد نتایج: 243 فیلتر نتایج به سال:
In this paper, we show a new approach for solving discrete floorplanning problems. Modules to be placed and the target architecture are modelled by periodic graphs. The objective is, to find a valid assignment of module nodes to slot nodes of the target architecture, such that a cost function on the placement will be minimized. We use an algorithm which is abstracted and derived from a traditio...
In nano-based microarchitectural design, achieving higher clock frequency is confronted with thermal restrictions especially with the presense of temperature-variant leakage power. While a module temperature depends both on power density and the thermal coupling with the neighboring blocks, thermal-aware floorplans have been introduced to reduce peak temperature. The major drawback is that the ...
Power density of microprocessors is increasing with every new process generation resulting in higher maximum chip temperatures. The high temperature of the chip greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling solutions significantly more expensive. The maximum temperature of a block in a chip depends not only on its own power density...
We propose a net-based hierarchical macrocell placement such that “net placement” dictates the cell placement. The proposed approach has four phases. 1) Net clustering and net-level floorplanning phase: A weighted net dependency graph is built from the input register-transfer-level netlist. Clusters of nets are then formed by clique partitioning and a net-cluster level floorplan is obtained by ...
Abstract As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are the most effective and popular techniques to reduce interconnect delay and are traditionally applied to post-layout optimization. As the SIA technology roadmap predicts, however, the number of interconnections...
This research paper investigates the influence of different initial design techniques on area, timing, and power aspects technology-mapped designs. As a practical case study, we undertake analysis 32-bit arithmetic logic unit (ALU) utilizing two distinct adder approaches. The ALU, fundamental component all processors, comprises three major units: Adder responsible for signed unsigned number add...
With the continued improvement of the nanometer IC technologies, large-scale mixed-size placement becomes a vital problem where there is a significant size variation between building modules and standard cells. Floorplanning techniques are very suitable to pack modules, but do not scale to hundreds of thousands of objects. Multilevel partitioning algorithms rapidly divide the large scale object...
He brought me into the field of VLSI CAD. His encouragement and guidance has been a tremendous help throughout my PhD study. The fruitful discussions with him have bloomed many unexpected and stimulating thoughts. Also the criticism from him has led to a higher quality of research work. discussion. Special thanks are due to Ruiqi Tian and Hua Xiang, who help me a lot in completing this disserta...
As semiconductor process technology relentlessly advances into deeper submicron feature sizes following the Moore’s Law, the cost of mask tooling is growing inexorably, up to 1, 1.5, and 3 million dollars for 90nm, 65nm, and 32nm process technology, respectively (LaPedus, 2006). Basically, the majority of smaller fabless integrated circuit (IC) design houses can hardly afford to have one mask s...
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