An architecture for a time interpolation circuit with an rms error of 25 ps has been developed in a 0.7m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage depend...

This paper is has addressed the Single Flexible Link Robot. The dynamical model is derived using Euler-Lagrange equation and then a proper controller is designed to suppress a  vibration based-on Input-Shaping (IS) method. But, IS control method is an open loop strategy. Due to the weakness of open loop control systems, a closed loop IS control system is proposed. The achieved closed loop c...

We stabilized the repetition rate of an optical frequency comb using a self-referenced phase-locked loop. The phase-locked loop generated its error signal with a fiber-optic delay-line interferometer that had a path-length difference of 8 m. We used the stabilized repetition rate to generate a 10 GHz signal with a single-sideband phase noise that was limited by environmental noise to -120  dBc/...

in this paper a new method is introduced and investigated for removing the destabilizing effects of time-delay parameter in control loops. the concept of the method is taken from the knowledge concerning the dynamic behaviour of irrational transfer functions (ir-tf), which is discussed and investigated elswhere in frequency response domain and is explained briefly here. ir-tfs, which are well c...

The tracking performance of non-linear amplifier based conventional second order phase locked loop (PLL) and charge pump phase locked loop have been examined numerically by solving the system equations in the presence of lognormal type of fading signal. Some analytical results for non-linear amplifier based conventional phase locked loop and charge pump phase locked loop are also incorporated t...

Two types of coherent delay-locked loops (DLL) are considered in this paper as delay trackers in multiuser CDMA receivers. The rst approach is based on the parallel interference cancellation (PIC) method. PIC based delay trackers require the estimation of channel parameters and data symbols of all users to construct the multiple-access interference (MAI) estimates. The other method is based on ...

A multiplying delay-locked loop (MDLL) for highspeed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filt...

Abstract A high-resolution clock phase shifter is implemented to adjust the of multiple clocks at 40 MHz, 80 or 640 MHz in ALTIROC chip. The has a coarse-phase and fine-phase achieve step size 97.7 ps an adjustable range 25 ns. fine delay unit based on Delay Locked Loop (DLL) operating MHz. fabricated 130 nm CMOS process. area 725 µm × 248 µm. Differential Non-Linearity (DNL) Integral (INL) are...