Vertical Double Diffused MOSFET (VDMOS) is an established technology for high-current power switching applications such as automotive circuits. The most serious failure mode is destructive damage during inductive switching, resulting from avalanche breakdown of the forward blocking junction in the presence of high current flow. Improving the ruggedness of the device is achieved by enhancing its...

We present an analytical model for the subthreshold characteristic of ultra-thin Independent Double-Gate transistors working in the ballistic regime. This model takes into account short-channel effects, quantization effects and source-to-drain tunneling (WKB approximation) in the expression of the subthreshold drain current. Important device parameters, such as off-state current or subthreshold...

This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CGD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide CGD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the re...

Meeting the timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, we present a novel technique to speed up gate-level timing simulation that is based on Structurally Synthesized Binary Decision Diagrams (SSBDD), which have alread...

A simple yet realistic MOS model, namely the a-power law MOS model, is introduced to include the carrier velocity saturation effect, which becomes eminent in short-channel MOSFET’s. The model is an extension of Shockley’s square-law MOS model in the saturation region. Since the model is simple, it can be applied for handling MOSFET circuits analytically and can predict the circuit behavior in t...

Meeting timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, we present a novel technique to speed up gate-level timing simulation that is based on Structurally Synthesized Binary Decision Diagrams (SSBDD), which have already fo...

Binary decision diagrams (BDD) have gained a wide acceptance as a mathematical model for representation and manipulation of Boolean functions in VLSI CAD. In this paper we consider a special kind of BDDs called Structurally Synthesized BDDs (SSBDDs), which have an important characteristic property of keeping information about circuit’s structure. Despite the fact that the SSBDD model itself is ...

Headstage preamplifiers and source followers are commonly used to study neural activity in behavioral neurophysiology experiments. Available commercial products are often expensive, not easily customized, and not submersible. Here we describe a method to design and build a customized, integrated circuit headstage for simultaneous 4-channel neural recording and 2-channel simulation in awake, beh...

In this paper, we find the relationship between mincut circuit partitioning and the initial (V, E) pairs distributed condition I entropy on the V-E plain. If a circuit has higher initial potential / entropy, under a nearly max-cut reservation, we have higher probability to aim the mincut. The proposed new method is called Interleaved Cutting Edge-Node Interleaved Sort for Leaching and Envelop (...

High frequency models of transistors are of interest because they have applications to computeraided design of high frequency circuits. When these models are derived, a problem encountered is that measured transistor S-parameters do not agree with the hybrid-π model. In this article, a simplified method is described to obtain an optimized classical hybrid-π model that predicts the measured S-pa...