Reversible digital technology can now start taking a more desirable direction for low dissipation of power, higher processing speeds. Here, we suggested the construction an 8-, 16-, 32-, 64-bit multiplier using carry-save adder, Kogge stone and HNFG adder with high operating speed proposed gate adder. The architecture device logic gates which are reversible be implemented Vedic multiplier. outp...

Addition is one of the fundamental arithmetic operations which are used extensively in many VLSI systems such as microprocessors and application specific DSP architectures. In this paper, the Significance Approximation Error Tolerant Carry Select Adder (SAET-CSLA) is constructed, which is efficient in terms of accuracy, power and area. While considering the elementary structure of an image proc...

In this paper the first code-disjoint totally self-checking carry-select adder is proposed. The adder blocks are fast ripple adders with a single NAND-gate delay for carry-propagation per cell. In every adder block both the sum-bits and the corresponding inverted sum-bits are simultaneously implemented. The parity of the input operands is checked against the XOR-sum of the propagate signals. Fo...

MOS current mode logic (MCML) techniques are usually used for high-speed applications such as high speed processors and multiplexers for optical transceivers. A new design of full adder is proposed based on MOS Current Mode Logic (MCML). It is a new alternative for designing a full adder. Using MCML logic, the power consumptions of circuits can be reduced to the effective level by supplying it ...

With the continuing trends to reduce the chip size and integrates multichip solution into a single chip solution it is important to limit the silicon area required to implement parallel FIR digital filter in VLSI implementation. The Need for high performance and low power digital signal processing is getting increased. Finite Impulse Response (FIR) filters are one of the most widely used fundam...

In’this paper, a new family of dynamic logic gates called Dualrail DataDriven Dynamic Logic (D4L) is introduced. In this logic family, the synchronization clock signal has been eliminated and correct precharge and evaluation sequmcing is maintained by appropriate use of data instances. The methodology and characteristics of d L are demonstrated in the design of a CLA 32-b adder and a 17-b high-...

Binary adders are the basic and vital element in the circuit designs. Prefix adders are the most efficient binary adders for ASIC implementation. But these advantages are not suitable for FPGA implementation because of CLBs and routing constraints on FPGA. This paper presents different types of parallel prefix adders and compares them with the Simple Adder. The adders are designed using Verilog...

Abstract: Modular adder is used in Residue Number System (RNS) addition. Moduli set with the form of 2-21(1≤ k≤ n-2) can offer excellent balance among the RNS channels for multi-channel RNS processing. In this paper, a Finite Impulse Response (FIR) filter using a novel algorithm and its Very Large Scale Integration (VLSI) implementation structure are proposed for modulo 2-2-1 adder. In the Modu...

We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary multiplication. One advantage of the ternary adder is that four instead of three inputs within a binary representation will be summed up. In this paper we will compare the complexity of binary against ternary multiplier...

In data processing processors, adder is a basic digital circuit. To perform any arithmetic operation, addition is the basic operation to perform. To compute fast arithmetic operations adder must be fastest. CSLA is the fastest adder when compare to RCA and CLA. From the structure of CSLA it is observed that there is a scope to reduce area further so that power can be lowered [3-4]. This paper p...