The tool to be presented in the panel deals with validation of VHDL descriptions at the early phase of the design of a digital system. Our approach consists in generating test data from a given VHDL behavioral description. The validation is achieved by comparing the results obtained using the simulation of the VHDL description within the test data and the results which should have been obtained...

This paper will describe the development of a prototype software toolbox that can analyze and process a Simulink block diagram model in order to produce a VHDL representation of the model. The derived VHDL model will consist of a combination of behavioural, RTL and structural definitions mapped directly from the Simulink model. This approach may enable a user to develop and simulate a digital c...

Hardware Description Languages (HDL) like VHDL are widely used to design and simulate with programmable logic devices. Simulation of very large scale integrated digital systems (VLSI) is of great importance as it assures system correctness and maximizes system performance ([4], [5], [9]). The utilization of parallel simulation introduces the problem of how to partition the logic gates and syste...

This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set o...

In hardware design of today, there is a growing usage of hardware design languages to speed up the time-to-market. As the design complexity grows, so does the simulation time. To solve this problem, several research groups have suggested the use of parallel computers to speed up simulation. This report surveys some of the issues involved when designing a parallel simulator for one of the more p...

VHDL is the one of the most important and widely used hardware description languages at this time. The increase in size and complexity of VHDL models necessitates the use of parallel and distributed algorithms to obtain acceptable simulation performance. We have investigated the use of optimistic distributed algorithms with VHDL simulation. Using an optimistic algorithm with VHDL introduces som...

In a top-down, language-based design methodology, requirements can be specified in an executable format, reducing the ambiguity typically encountered with written requirements, and serving as the starting point for the evolution of more detailed requirements and design specifications. As part of the Rapid Prototyping of Application Specific Signal Processors (RASSP) program, a VHDL executable r...

We present a mathematical de nition of a hardware description language that admits a semantics-preserving translation to a subset of VHDL. The language is based on the VHDL model of event-driven simulation and includes behavioral and structural circuit descriptions, the basic VHDL propagation delay mechanisms, and both zero and nonzero delays. It has been formally encoded in the computational l...