We present a novel set of reversible modular multipliers applicable to quantum computing, derived from three classical techniques: 1) traditional integer division, 2) Montgomery residue arithmetic [1], and 3) Barrett reduction [2]. Each multiplier computes an exact result for all binary input values, while maintaining the asymptotic resource complexity of a single (non-modular) integer multipli...

Topological color codes defined by the 4.8.8 semiregular lattice feature geometrically local check operators and admit transversal implementation of the entire Clifford group, making them promising candidates for fault-tolerant quantum computation. Recently, several efficient algorithms for decoding the syndrome of color codes were proposed. Here, we modify one of these algorithms to account fo...

A low-leakage 2×VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit composed of the siliconcontrolled rectifier (SCR) device and new ESD detection circuit, realized with only thin-oxide 1× VDD devices, has been proposed with consideration of gate leakage current. By reducing the voltage across the gate oxides of the devices in the ESD detection circuit, the whole power-rail ESD ...

The design and optimization of realistic architectures for fault-tolerant quantum computation requires error models that are both reliable and amenable to large-scale classical simulation. Perhaps the simplest and most practical general-purpose method for constructing such an error model is to twirl a given completely positive channel over the Pauli basis, a procedure we refer to as the Pauli t...

This paper deals with reconfigurable back-to-back converter topology and control orders in Wind Energy Conversion Systems (WECS). A typical WECS with Doubly Fed Induction Generator (DFIG) in balanced conditions is concerned. Based on the classical topology, a fault tolerant converter without any redundancy has been studied. The presented fault tolerant topology allows a “five-leg” structure wit...

An arbitrarily reliable quantum computer can be efficiently constructed from noisy components using a recursive simulation procedure, provided that those components fail with probability less than the fault-tolerance threshold. Recent estimates of the threshold are near some experimentally achieved gate fidelities. However, the landscape of threshold estimates includes pseudothresholds, thresho...

Genetic Algorithm based automatic evolution of fault tolerant digital circuits has been examined at three different levels. At the first level, multiple working designs are automatically generated, offline, without additional human design effort and each is documented with the unused resources information. This information is used for fault tolerance. Depending on the number of versions generat...

An ionizing radiation-tolerant CMOS active pixel sensor (APS) image sensor test chip was designed employing the physical design techniques of enclosed geometry and -channel guard rings. The test chip was fabricated in a standard 0.35m CMOS process that has a gate-oxide thickness of 7.0 nm. It was irradiated by a -ray source up to a total ionizing radiation dose level of approximately 30 Mrd (Si...

Transient (soft) faults due to particle strikes and other environmental and manufacturing effects are a frequent cause of failure in ICs. We propose a general, technology-independent model called single transient fault (STF) model to represent transient faults and errors in logic circuits. It is defined in terms of a temporary stuck-at fault and its associated circuit state. STFs can be used to...

The delay dependence on temperature reverses at increasingly larger supply voltages as technology scales into the nanometer regime, causing delay to decrease as temperature increases. This reversal can be problematic for variation-tolerant systems using critical path replicas to determine delay guardbands, as delay may no longer indicate when the system is in danger of thermal runaway. Adaptive...