To sustain transistor scaling beyond lateral 7 nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. overcome roadblocks logic cell design using this emerging technology, work explores compact modeling 3D GAA-JLNTs based on physics transport. The model features an explicit continuous analytical form drain current ...

In this paper, the subthreshold swing was observed when stacked high-k gate oxide used for a junctionless double (JLDG) MOSFET. For purpose, model presented using series-type potential derived from Poisson equation. The results of in paper were good agreement with two-dimensional numerical values and those other papers. Using model, variation channel length, silicon thickness, dielectric consta...