a mathematical modelling for more-winding single-phase transformer is presented. the incidence matrix-which gives the informations about the connection of the ends of the windings between the nodes-is multiplied leftside and rightside with the inverse of the inductance matrix of the more winding transformer. the result is a matrix which gives the relationship between nodes potentials and nodes ...

We are starting to investigate a novel multiplexable readout method that can be applied to a large class of superconducting pair-breaking detectors. This readout method is completely different from those currently used with STJ and TES detectors, and in principle could deliver large pixel counts, high sensitivity, and Fano-limited spectral resolution. The readout is based on the fact that the k...

A numerical procedure for extracting parasitic circuit elements using a quasi-static field solver, as part of the Virtual Test Bed (VTB), is discussed. The parasitic inductance and capacitance values obtained from the model are compared to measured values from a low-inductance Power Electronic Building Block (PEBB) module, designed and constructed at Harris Semiconductor.

This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the undesirable effects of on-chip inductance are higher interconnect coupling noise and substrate coupling, challenges for accurate extraction, the required modifications of the infrastructure of CAD tools, and the inevitably slowe...

In this work, 4 structural configurations are proposed, and analyzed, to be used as linear switched reluctance generators with tubular topology. For the 4 models under assessment, inductance change with the mover part position is assessed to quantify the machine capabilities as generator. This evaluation is supported by a 2D FEM analysis based software through which are determined the inductanc...

Abstract Accurate integrity assessment of on-chip clock lines is difficult without any a priori knowledge about their inductance at an early stage in the clock design process. This paper introduces an efficient approach to estimate the bounds of on-chip clock wire inductance at the very beginning of the design stages. With this information, more accurate waveforms along the clock distribution n...

A multilevel modeling approach was developed for effective prediction for performance parameters of Switched Reluctance Machine. In this approach each system is described by its most efficient model. This paper addresses the problem of multilevel modeling applied to Switched Reluctance Machine (SRM). Using field analysis magnetic characteristics and inductance profile of the SRM are obtained. T...