Noise in digital logic circuits does not reduce with the scaling down of CMOS devices. The conventional CMOS design does not provide noise immunity when the circuits are operated in the sub threshold region. In order to enhance the performance of the circuit and to handle the errors caused due to noise that are random and dynamic in nature, a cost effective probabilistic based noise tolerant ci...

We consider fault-tolerant computation with formulas composed of noisy Boolean gates with two input wires. In our model all gates fail independently of each other and of the input. When a gate fails, it outputs the opposite of the correct output. It is known that if all gates fail with probability at least β2 = (3− √ 7)/4 ≈ 8.856%, faulttolerant computation is not possible. On the other hand, i...

The quantum logic gates used in the design of a computer should be both universal, meaning arbitrary computations can performed, and fault-tolerant, keep errors from cascading out control. A number no-go theorems constrain ways which set fault-tolerant universal. These are very restrictive, conventional wisdom holds that universal gate cannot implemented natively, requiring us to use costly dis...

Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, promising alternative to CMOS technology due to faster speed, smaller size, lower power consumption, higher scale integration and higher switching frequency. Also, power dissipation is the main limitation of all the nano electronics design techniques including the QCA. Researchers have proposed the various mechanisms t...

ERROR-free computation is an unattainable ideal, yet our world now contains many computers that appear error-free to their users. That such things are possible is explained by sophisticated theorems that demonstrate the possibility of efficiently reducing computational errors introduced by reasonably well-behaved noise. My thesis is about the problem of determining whether noise in prototype qu...

Recently, nonadiabatic geometric quantum computation has received much attention due to its fast manipulation and intrinsic error-resilience characteristics. However, obtain universal control, only limited special evolution paths have been proposed, which usually require longer gate-time more operational steps, thus lead lower quality of the implemented gates. Here, we present an effective sche...

This paper describes the impact of crosstalk noise on low power design techniques based on voltage scaling. I t is shown that this power saving strategy aggmvates the crosstalk noise problem and reduces circuit noise immunity. A new energy-eficient, noise-tolerant dynamic circuit technique is presented to address this problem. In a 0.35pm CMOS technology and at a given supply voltage, the propo...

This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35m CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1 8 (for an AND gat...

This pedagogical review presents the proof of the Solovay-Kitaev theorem in the form of an efficient classical algorithm for compiling an arbitrary single-qubit gate into a sequence of gates from a fixed and finite set. The algorithm can be used, for example, to compile Shor's algorithm, which uses rotations of π/2 k , into an efficient fault-tolerant form using only Hadamard, controlled-not, a...

Most work in quantum circuit optimization has been performed in isolation from the results of quantum fault-tolerance. Here we present a polynomial-time algorithm for optimizing quantum circuits that takes the actual implementation of fault-tolerant logical gates into consideration. Our algorithm re-synthesizes quantum circuits composed of Clifford group and T gates, the latter being typically ...